Semiconductor Memory Test Circuit Using Data Pad Fail Status
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Solution Overview
Problem
Conventional semiconductor memory devices require additional test pins for testing, which increases chip size and test time, especially when testing multiple memory cells in a module or system environment, and there is a need for a more efficient method to reduce these constraints.
Innovation Solution
A semiconductor memory device with a test mode control unit that compares data between first and second memory cells, using a path selection unit to transfer data between memory cells and data pads, and a fail detection unit to output fail signals, allowing for reduced test time and elimination of additional test pins by denoting fail status through data pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional test pins are added to output comparison results, then test results can be output, but chip size increases
Solution Approach 1:
The data pads are made multi-functional by enabling them to serve both as normal data I/O interfaces and as test result output pins. During test mode, the path selection unit redirects test data through the data pads, allowing them to display comparison results without requiring separate dedicated test pins, thus eliminating the need for additional pins while maintaining test capability.
2Productivity
If conventional parallel test scheme is used with additional test pins, then multiple memory cells can be tested, but test time increases
Solution Approach 1:
The path selection unit is pre-configured to automatically redirect test data to both first and second memory cells simultaneously during test mode. This preliminary setup enables parallel testing of multiple memory cells using the same test data without requiring sequential operations, thereby reducing test time while maintaining the ability to test multiple cells.
Solution Approach 2:
The test mode control unit continuously monitors and compares data from both memory cells during the test operation, maintaining continuous useful action throughout the test process. This continuous comparison and monitoring enables efficient parallel testing without idle periods, reducing overall test time while testing multiple cells simultaneously.
3Productivity
If test data are transferred to both first and second memory cells, then parallel testing is enabled, but device complexity increases
Solution Approach 1:
The path selection unit acts as an intermediary component that simplifies the data transfer control by automatically directing test data to both first and second memory cells during test mode. This intermediary unit handles the complexity of simultaneous data distribution, enabling parallel testing capability without significantly increasing overall device complexity through its modular and controlled approach.
Data Source
AI summary
A semiconductor memory device includes a plurality of banks, each including a plurality of first memory cells and a plurality of second memory cells, a first input/output unit configured to transfer first data between the first memory cells and a plurality of first data pads, a second input/output unit configured to transfer second data between the second memory cells and a plurality of second data pads, a path selection unit configured to transfer the first data which are input through the first data pads, to both the first and second memory cells, during a test mode, and a test mode control unit configured to compare the first data of the first and second memory cells, and to control the first data pads to denote a fail status based on a comparison result, during the test mode.