Semiconductor Memory Test Decoding Select Circuit
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Solution Overview
Problem
In semiconductor memory apparatuses, it is challenging to discern defective lines due to extensive electrical coupling, making it difficult to identify and substitute defective bit or word lines effectively.
Innovation Solution
The semiconductor memory apparatus includes a test decoding select circuit that generates enable signals for normal, redundancy, and dummy lines, allowing selective enabling of these lines in response to an address and test signals, facilitating easy identification of defective lines during testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a large number of lines are electrically coupled to each other, then the semiconductor memory apparatus can store and access data efficiently, but it becomes difficult to discern defective lines when a line defect occurs
Solution Approach 1:
The patent segments the line selection function by introducing separate decoding enable signals for normal lines (N_en), redundancy lines (R_en), and dummy lines (D_en). This segmentation allows independent control and testing of different line types, making defective line identification easier while maintaining efficient data storage and access through the integrated line structure.
2Reliability
If redundancy lines and dummy lines are disposed in the semiconductor memory apparatus, then defective lines can be substituted or protected, but the device complexity increases due to multiple line types and decoding circuits
Solution Approach 1:
The patent implements multi-functionality by designing the decoding enable signal generation circuit to control normal, redundancy, and dummy lines through a unified testing mechanism. The test entry signal (TM_entry) and test code (TM_code) can selectively activate different line types, allowing a single decoding circuit structure to serve multiple functions: normal operation, redundancy substitution, and dummy line testing.
3Difficulty of detecting and measuring
If separate decoding enable signals are generated for normal, redundancy, and dummy lines, then defective lines can be easily identified during testing, but the test decoding select circuit complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-organizing the decoding enable signal generation logic in the test decoding select circuit. The circuit is designed with dedicated logic paths that respond to specific test codes to generate appropriate enable signals for normal, redundancy, or dummy lines. This preliminary structuring of the testing mechanism enables easy defective line identification without requiring complex runtime decision-making.
Data Source
AI summary
A semiconductor memory apparatus includes a test decoding select circuit. The test decoding selective circuit is configured to generate a normal decoding enable signal, a redundancy decoding enable signal, and a dummy decoding enable signal, in response to a test entry signal, a test code, and an active signal.