Memory Test Data Path with Delayed Read-Write Alternation

Solution Overview

Problem

Embedded memory systems face challenges in parallel testing due to high power consumption, which can lead to increased voltage levels and potential damage during testing, limiting the number of memory units that can be tested simultaneously within a power budget.

Innovation Solution

A memory data path architecture that groups memory units into two groups, where one group performs write operations and the other group performs read operations with a time cycle delay, reducing overall power consumption by alternating these operations and synchronizing test result signals without lag, allowing more units to be tested in parallel within the same power budget.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If memory units are tested in parallel without operation alternation, then testing speed is improved, but power consumption increases leading to voltage spikes and potential component damage

Engineering Contradiction:

Improvetesting speedVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSPower

Solution Approach 1:

The patent implements periodic alternation between write operations and read operations across different memory unit groups. First group performs write operations while second group performs read operations, then they switch in subsequent time cycles. This periodic action distributes the power consumption peaks over time, preventing simultaneous high power draw from all memory units, thus resolving the contradiction between fast parallel testing and power consumption control.

Inventive Principle:

Principle #19Periodic action

2Productivity

If more memory units are tested in parallel, then testing efficiency is improved, but power consumption increases beyond the power budget

Engineering Contradiction:

Improvetesting efficiencyVSAvoidpower budget

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent divides the memory units into multiple groups (first group and second group) that are tested in parallel. Each group is further segmented to perform different operations (write or read) at different time cycles. This segmentation allows more memory units to be tested simultaneously while controlling the power consumption of each group, enabling the system to test more units in parallel without exceeding the overall power budget.

Inventive Principle:

Principle #1Segmentation

3Reliability

If write and read operations are performed simultaneously across all memory units, then testing completeness is improved, but voltage levels increase causing potential damage

Engineering Contradiction:

Improvetesting completenessVSAvoidvoltage spikes

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent implements periodic alternation between write operations and read operations across different memory unit groups. First group performs write operations while second group performs read operations, then they switch in subsequent time cycles. This periodic action distributes the power consumption peaks over time, preventing simultaneous high power draw from all memory units, thus resolving the contradiction between fast parallel testing and power consumption control.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The patent employs delay elements that introduce controlled time delays in signal paths to synchronize operations and prevent simultaneous peak power consumption across all memory units. This beforehand cushioning through timing control ensures that not all memory units draw peak power at the same time, cushioning against voltage spikes that could cause component damage while maintaining testing completeness.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS11715544B2System and method for low power memory test

Publication Date: 2023.08.01 TEXAS INSTRUMENTS INC

AI summary

An apparatus includes a first group of memory units and a second group of memory units coupled to a first data path and a second data path coupled to a controller, a first delay element on the first data path coupled to the second group of memory units and configured to send, from the controller to the second group of memory units, signals for write and read operations in a sequence of time cycles delayed by a time cycle with respect to the first group of memory units, and a second delay element on the second data path and coupled to the first group of memory units and configured to send, from the first group of memory units to the controller, test result signals delayed by a time cycle, the delayed test result signals having a matching delay to the delayed write and read operations.