Memory Test Circuit Using Divided I/O Buffers and Logic Gates
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Solution Overview
Problem
Testing hyper-multi I/O DRAMs is challenging due to limited I/O driver-comparator resources and probe card limitations, making it difficult to effectively test and repair defective memory cells without increasing the number of input and output pads.
Innovation Solution
A memory configuration with divided input and output buffers into even-numbered and odd-numbered groups, utilizing at least two data input pads and one data output pad, along with logic gates for test operations, allows for efficient testing with reduced I/O pads by performing logic operations on outputs to determine cell defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the number of I/O ports is significantly increased to achieve hyper-multi I/O memory, then bandwidth between logic and memory on the chip is improved, but testing difficulty increases due to limited ATE I/O driver-comparator resources and probe card needle resources
Solution Approach 1:
The patent divides the I/O buffers into even-numbered and odd-numbered groups, allowing test data to be written through separate paths and read back through combined logic gates. This segmentation enables testing of hyper-multi I/O memory with fewer physical test pads by logically organizing the I/O resources into manageable groups that can be tested in parallel.
2Difficulty of detecting and measuring
If the number of pads for testing is increased to test hyper-multi I/O DRAM, then testing capability is improved, but the memory configuration becomes unrealistic due to lack of additional pads
Solution Approach 1:
The patent merges the test data paths by combining outputs from even-numbered and odd-numbered I/O buffers through logic gates (XOR and NOR gates) to produce a single test result. This merging allows comprehensive testing of all I/O ports while using only two data input pads and one data output pad, eliminating the need for additional physical pads.
Solution Approach 2:
The logic gate circuitry serves multiple functions: it combines test data from different I/O buffer groups, performs logical operations to detect defects, and generates test results that indicate the status of multiple I/O ports simultaneously. This multi-functionality allows a single test structure to handle hyper-multi I/O testing without requiring dedicated test pads for each I/O port.
3Productivity
If I/O buffers are divided into even-numbered and odd-numbered groups with separate test paths, then testing efficiency is improved, but circuit complexity increases due to additional logic gates
Solution Approach 1:
The patent uses identical logic gate structures (XOR gates for even and odd groups, followed by a NOR gate) to process test data from different I/O buffer groups. This copying of the logic structure allows parallel processing of multiple I/O groups while maintaining a regular, predictable circuit pattern that simplifies design and analysis despite the increased number of components.
Data Source
AI summary
A memory with a test function and a method thereof. The memory includes a memory array having cells, input buffers divided into even- and odd-numbered groups and output buffers divided into even- and odd-numbered groups; at least two data input pads, respectively providing test data to the cells through the even-numbered and the odd-numbered input buffers; a first and a second logic gates, respectively performing a first logic operation on outputs of the even-numbered and odd-numbered output buffers; a third logic gate, performing a second logic operation on outputs of the first and the second logic gates; and at least one data output pad, coupled to an output of the third logic gate for providing a test result of the cells.