Transaction-Level Memory Test Engine Bypassing Address Decoder
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Solution Overview
Problem
Traditional memory testing methods face challenges in reliably detecting failures due to the need for specific power supply noise, crosstalk, and inter-symbol interference conditions, which are difficult to create, especially in memory array cells, and require complex and costly hardware configurations.
Innovation Solution
A test engine coupled to a memory controller that provides memory access transactions, allowing for deterministic and configurable testing at the transaction level, bypassing the memory address decoder to precisely target specific memory locations and generate specific command sequences, enabling precise control over memory operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional hardware FSMs are used for memory testing, then testing can operate closer to the memory controller avoiding multiple processing levels, but the hardware becomes prohibitively expensive and complex to perform all desired testing functions
Solution Approach 1:
The patent implements a universal test engine that can perform multiple types of memory tests through a single hardware structure. The test engine is designed to execute various test algorithms and patterns, replacing the need for multiple dedicated hardware FSMs. This multi-functional approach maintains testing reliability while significantly reducing hardware complexity and cost.
Solution Approach 2:
The patent uses a software-based test engine that replicates the functionality of hardware FSMs. By copying the test logic into software that runs on the memory controller, the system achieves the same testing capabilities without requiring complex dedicated hardware circuits. This software implementation can be updated and reconfigured without hardware changes.
2Adaptability or versatility
If software testing mechanisms are used, then the system can be flexible and adaptable, but the software goes through multiple levels of processing and scheduling that result in out-of-order execution and cannot precisely target memory areas
Solution Approach 1:
The patent introduces a test engine as an intermediary component that sits between the software test algorithms and the memory controller. This test engine receives high-level test instructions from software and translates them into precise memory access commands. The intermediary ensures that software flexibility is maintained while achieving precise address targeting by directly generating memory controller commands without going through multiple processing levels.
3Ease of manufacture
If traditional testing methods are used, then hardware costs are reduced, but the ability to detect subtle I/O failures and memory array cell failures is insufficient due to inability to create specific failure conditions
Solution Approach 1:
The patent implements a dynamic test engine that can adaptively adjust test parameters, patterns, and sequences based on the specific memory device being tested. The test engine can dynamically change access patterns, data values, and timing to create the specific conditions needed to trigger subtle failures. This dynamic approach maintains manufacturing simplicity while significantly improving failure detection capability compared to static traditional methods.
Data Source
AI summary
A memory subsystem includes a test engine coupled to a memory controller that can provide memory access transactions to the memory controller, bypassing a memory address decoder. The test engine hardware is configurable for different tests. The test engine identifies a range of addresses through which to iterate a test sequence in response to receiving a software instruction indicating a test to perform. For each iteration of the test, the test engine, via the selected hardware, generates a memory access transaction, selects an address from the range, and sends the transaction to the memory controller. The memory controller schedules memory device commands in response to the transaction, which causes the memory device to execute operations to carry out the transaction.