Memory Test Engine via Structural Primitives
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Solution Overview
Problem
Current memory testing methods require manual extraction of physical topology information from CAD layout files to generate data sequences for testing and fault diagnosis, which is inefficient and time-consuming, especially when dealing with different sizes and types of memory ICs.
Innovation Solution
A computer-implemented method that uses a library of procedures to translate between physical and logical models of memory arrays, allowing for automatic generation of data sequences and fault diagnosis without analyzing the entire CAD layout file, by defining structural primitives and scrambling information specific to the memory design family.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If manual extraction of physical topology information from CAD layout files is used, then fault diagnosis and testing can be performed, but the process is inefficient and time-consuming
Solution Approach 1:
The patent introduces an intermediate level structural description as a mediator between the physical CAD layout and the logical test model. This intermediate representation automatically captures physical topology information (scrambling, twisting, straps) and translates it into testable logical models, eliminating the need for manual extraction while maintaining accuracy in fault diagnosis and testing.
Solution Approach 2:
The patent replaces the manual mechanical process of extracting topology information from CAD files with an automated computational system. The system automatically analyzes CAD layouts, extracts physical topology, generates structural descriptions, and creates test engines, substituting human manual work with automated algorithms and software tools.
2Measurement precision
If analysis of entire CAD layout files is performed, then complete physical topology information is obtained, but CAD resources are consumed and complexity increases
Solution Approach 1:
The patent extracts only the essential physical topology information needed for testing from the comprehensive CAD layout. By identifying and extracting key features (scrambling patterns, twisting configurations, strap locations) rather than processing the entire CAD file, the system achieves sufficient accuracy for fault diagnosis while reducing computational complexity and resource consumption.
Solution Approach 2:
The patent segments the physical topology analysis into distinct structural primitives (address scrambling, data scrambling, bitline twisting, straps). Each primitive is independently extracted and represented, allowing the complex physical topology to be broken down into manageable components that can be processed efficiently and recombined for test engine generation.
3Adaptability or versatility
If different memory designs require custom test engines, then testing can be tailored to specific requirements, but development time increases
Solution Approach 1:
The patent performs preliminary action by automatically generating the intermediate structural description and test engine model before actual testing begins. The system pre-processes the CAD layout to extract topology information and creates the complete test engine configuration in advance, so that when testing starts, the engine is ready to execute immediately without additional development time.
Solution Approach 2:
The patent handles adaptability through parameter changes by allowing the same automated system to accommodate different memory designs through configurable parameters. The structural description framework can be adjusted to match different memory architectures (DRAM, SRAM, crossbar) by modifying a set of parameters rather than requiring custom development for each design type.
Data Source
AI summary
A computer-implemented method for creating an integrated circuit, IC, test engine for testing a proposed IC memory array using new memory structural model. An IC designer inputs the number of words that can be stored and a column multiplexer ratio in a proposed IC memory array. A selection of one or more procedures is made from a library of computer-readable procedures. Each of the procedures is to produce one or more structural primitives that describe certain physical layout features of the proposed IC memory array, without analyzing a CAD layout file of the proposed IC memory array. The library of procedures as a whole translates between a physical model of a family of IC memory arrays and a user interface model of the family. A data background, DB, pattern is produced to be used by the test engine in testing the proposed IC memory array. This is done by executing the selected one or more procedures, wherein these procedures take as input the received number of words and column multiplexer size. Other embodiments are also described.