Memory Test Output via Separate Terminals for Better Eye Margin

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Solution Overview

Problem

Connecting a test device to the data connection terminal of a memory device introduces additional loading and signal degradation, particularly in high-speed memory devices like UFS 4.0, making accurate testing challenging due to narrowed eye margins.

Innovation Solution

Utilizing unused connection terminals and incorporating a serializer to convert sampled data into serial data, outputting it through separate terminals, thereby reducing data transfer speed and increasing eye margin.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a test device is connected to the data connection terminal of the memory device, then testing can be performed, but additional loading and signal degradation occur, narrowing the eye margin

Engineering Contradiction:

Improvetesting accuracyVSAvoidsignal degradation

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces an intermediary testing mode where the memory device itself generates test data and outputs it through a separate terminal (CMD or ADDR) rather than using the data connection terminal. This mediator approach allows testing to occur without the test device directly loading the data pins, thus maintaining signal integrity while enabling verification of memory device functionality.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If data is transmitted through the data connection terminal at high speed, then data transfer performance is improved, but signal degradation increases and eye margin narrows

Engineering Contradiction:

Improvedata transfer speedVSAvoidsignal degradation

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent segments the testing function from the normal data transmission path. Instead of using the high-speed data connection terminal for testing, it utilizes separate terminals (CMD or ADDR) that are not subject to the same high-speed signaling requirements. This segmentation allows the data connection terminal to maintain its high-speed performance while the testing function operates through a different, less demanding pathway.

Inventive Principle:

Principle #1Segmentation

3Adaptability or versatility

If the memory device operates in normal mode, then data exchange functionality is maintained, but testing capability is limited

Engineering Contradiction:

Improvedata exchange capabilityVSAvoidtesting functionality

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements a universal testing approach where the memory device uses its existing connection terminals (CMD or ADDR) for dual purposes: normal operation and testing. By making the connection terminals multi-functional, the device can switch between data exchange mode and testing mode without requiring dedicated separate terminals, thus maintaining adaptability while adding testing capability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250391492A1Memory device and testing method for memory device

Publication Date: 2025.12.25 SAMSUNG ELECTRONICS CO LTD

AI summary

A memory device includes a plurality of mode registers storing a plurality of status codes; a data input/output circuit that receives one status code of the plurality of status codes from one of the plurality of mode registers and samples the one status code to generate sampled data and transmit the sampled data to the serializer; and a serializer that receives the sampled data from the data input/output circuit, converts the sampled data into serial data, and outputs the serial data through a first connection terminal separate from a data connection terminal configured to exchange access data.