Memory Test Fail Analysis via Real-Time Data Filtering
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Solution Overview
Problem
Conventional Automated Test Equipment (ATE) systems for memory devices face challenges in efficiently capturing and analyzing error data due to high memory storage and processing requirements, leading to increased costs and latency, especially as memory sizes grow.
Innovation Solution
Implementing real-time compression and analysis hardware that filters out critical failure information in multiple passes, eliminating the need for large bitmap memory storage and enabling real-time redundancy and failure analysis, thereby reducing storage and computational resource needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ATE systems capture entire bitmap arrays for all DUTs in parallel, then complete error information is obtained for analysis, but memory storage requirements and processing costs become exceedingly high
Solution Approach 1:
The patent extracts only the critical failure-related information from the complete bitmap arrays using filtering hardware. Instead of storing and processing entire bitmaps, the system identifies and extracts only the failing bit positions and their addresses, dramatically reducing memory storage requirements while maintaining complete error information for analysis
Solution Approach 2:
The patent segments the error capture and analysis process into multiple sequential passes rather than requiring parallel processing of complete bitmaps. The testing is divided into chunks or segments that are processed independently, with failure information accumulated across passes, reducing peak memory requirements
2Loss of information
If conventional ATE systems store complete bitmaps for all DUTs, then all error information is available for post-processing analysis, but processing time and computational resources increase significantly
Solution Approach 1:
The patent performs preliminary filtering and identification of failure information during the testing passes themselves, rather than waiting for post-processing. The filtering hardware identifies and flags failing bits as they are tested, preparing the data in advance for efficient analysis without requiring later re-examination of complete bitmaps
Solution Approach 2:
The system extracts only the essential failure information (failing bit positions and addresses) during testing, eliminating the need to store and process redundant passing bit information. This extraction occurs sequentially during multiple passes, reducing both storage and subsequent processing time
3Productivity
If larger memory sizes are used in ATE systems to capture bitmaps from multiple DUTs, then more DUTs can be tested in parallel, but tester hardware cost increases
Solution Approach 1:
The patent replaces expensive, large-capacity bitmap storage memory with smaller, more economical filtering hardware and sequential processing logic. The system uses modest memory resources combined with intelligent filtering to achieve the same functional outcome, reducing hardware cost while maintaining productivity
Solution Approach 2:
The patent implements dynamic sequential processing where the system adapts its operation across multiple testing passes, accumulating failure information incrementally. This dynamic approach allows the same hardware resources to handle increasing numbers of DUTs by processing them in sequences rather than requiring proportionally larger parallel memory capacity
Data Source
AI summary
A method for testing memory devices under test (DUTs) using automated test equipment (ATE) is presented. The method comprises retrieving a portion of raw test data from a memory device under test (DUT). It also comprises comparing the portion of raw test data with expected test data to determine failure information, wherein the failure information comprises information regarding failing bits generated by the memory DUT. Next, the method comprises utilizing paging to transfer data comprising the failure information to a filtering module and filtering out the failure information from transferred data using the filtering module. Further, it comprises updating a fail list using the failure information, wherein the fail list comprises address information for respective failing bits within the memory DUT. Finally, it comprises repeating all the prior steps for the next block of raw test data.