Memory Die Test Coverage Using Failure Bit Address Analysis
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Solution Overview
Problem
Existing memory testing methods struggle to determine effective testing coverage and stability, leading to inefficiencies and potential defects in memory dies.
Innovation Solution
Utilizing multiple independent testing programs to identify common and different failure bit addresses, determining testing coverage based on these addresses, and optimizing testing items to improve yield and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple independent testing programs are used to test memory dies, then testing coverage and reliability are improved, but testing time and complexity increase
Solution Approach 1:
The patent applies preliminary action by performing multiple independent testing programs on memory dies before final classification. The failure bit information from each test is collected and analyzed in advance to determine common and different failure addresses, enabling more reliable defect identification before shipment decisions are made.
Solution Approach 2:
The patent segments the testing process into multiple independent testing programs, each targeting different aspects of memory die functionality. By dividing the comprehensive testing into separate programs and then analyzing the combined results, the system achieves higher reliability while managing complexity through structured segmentation.
2Reliability
If multiple independent testing programs are used to test memory dies, then testing coverage is improved, but device complexity increases
Solution Approach 1:
The patent implements universality by designing multiple independent testing programs that can be applied to various types of memory dies using the same basic framework. Each testing program serves multiple purposes: identifying failure bits, determining common failure addresses across tests, and providing data for coverage analysis, thereby reducing overall system complexity.
Solution Approach 2:
The patent uses feedback mechanisms where the results from each independent testing program are fed into a centralized analysis system. The failure bit information from multiple tests is compared and analyzed to identify common and different failure addresses, allowing the system to adaptively determine testing coverage and improve reliability through iterative feedback.
3Measurement precision
If comprehensive testing with multiple programs is performed, then defect detection accuracy is improved, but manufacturing cost increases
Solution Approach 1:
The patent replaces extensive mechanical/comprehensive physical testing with a more efficient information-based approach. By using multiple independent testing programs that generate failure bit information, and then analyzing this data to identify common and different failure addresses, the system achieves high defect detection accuracy while reducing the need for redundant comprehensive testing, thereby lowering manufacturing costs.
Data Source
AI summary
Disclosed is a method for determining a memory stability and a testing coverage. The method includes: providing multiple testing programs, for testing each memory die by using one of the testing programs to generate a failure bit information of each memory die; acquiring the failure bit information of each memory die tested with the each testing program; acquiring a failure bit address information of each memory die tested with each testing program based on the failure bit information of each memory die; acquiring a common failure bit address of the testing programs based on the failure bit address information of each memory die, or acquiring a different failure bit address of each testing program based on the failure bit address information of each memory die; and determining a testing coverage based on the common failure bit address, or determining a testing coverage based on the different failure bit address.