Memory Test Scheduling to Reduce Peak Current and IR Drop
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Solution Overview
Problem
Parallel memory testing in SoC designs leads to peak current-induced voltage drops (IR drop) and increased test costs due to excessive localized current demands, potentially rejecting or downgrading good dice and requiring additional power supplies.
Innovation Solution
Optimize memory test sequencing by creating scheduling buckets with serially executed test sequences, reordering them based on physical characteristics to reduce local IR drops and overall peak current demands, using algorithms like bin packing and greedy search to maximize physical separation of memory groups.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memories are tested in parallel, then test time is reduced, but peak current increases causing voltage drops and power supply issues
Solution Approach 1:
The patent applies dynamic scheduling by adjusting the start times of test sequences based on power consumption profiles and physical distances. Instead of static parallel or serial execution, the system dynamically determines optimized start times to balance test efficiency with power consumption constraints, allowing memories to be tested in parallel when power constraints are satisfied and serially when they are not.
2Productivity
If memories are tested in parallel, then test time is reduced, but voltage drops cause good dice to be rejected or downgraded
Solution Approach 1:
The patent applies preliminary anti-action by pre-calculating power consumption profiles and physical distances between memory groups, then using this information to proactively schedule test sequences in a way that prevents voltage drops before they occur. The system anticipates power consumption patterns and adjusts scheduling to avoid conditions that would cause voltage drops and false rejections of good dice.
3Power
If additional power supplies are added to handle peak current, then power supply stability is improved, but test cost increases
Solution Approach 1:
The patent applies parameter changes by optimizing the start times of test sequences based on power consumption profiles and physical distances. This scheduling optimization changes the temporal parameters of test execution to smooth out peak current demands, thereby maintaining power supply stability without requiring additional power supply infrastructure or increasing test costs.
Data Source
AI summary
A method for physical-aware power profile optimization during memory test includes creating a plurality of scheduling buckets, wherein each scheduling bucket includes one or more sequentially executed test sequences, each test sequence controlled by a respective Built-In Self-Test (BIST) controller, each test sequence including a respective unoptimized start time and a respective execution time, and a respective combined duration of the execution times of each respective scheduling bucket being less than or equal to a test time budget. A power profile is optimized by determining a respective optimized start time of at least one test sequence from at least a physical distance between two groups of memories controlled by respective BIST controllers. The respective optimized start time is assigned to the at least one test sequence.