Memory Performance Test Circuit Using Loop Signal Propagation
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Solution Overview
Problem
Existing memory testing methods, such as BIST, increase the size and reduce the performance of integrated circuits due to the added complexity and cost of internal test circuits.
Innovation Solution
A memory with a test circuit comprising a looped chain of test cells that mimic the electrical behavior of memory cells, allowing for performance evaluation by measuring signal propagation, and optionally including additional inverters and access transistors to match memory cell behavior, with an inhibition circuit to conserve energy during non-testing phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If internal test circuits are added to the memory for performance testing, then the ability to test memory cell performance is improved, but the silicon surface area increases and performance deteriorates
Solution Approach 1:
The patent merges the test circuit functionality with the existing memory cell structure by using the same bit lines, word lines, and memory cell layout. The test mode is activated by controlling existing memory cells to function as test elements, eliminating the need for separate dedicated test circuitry and thus avoiding additional silicon surface area consumption.
Solution Approach 2:
The patent makes the memory cells serve dual purposes: they function as both storage elements during normal operation and as test elements when test mode is activated. By controlling the state of memory cells and using the same physical infrastructure for both modes, the system achieves multi-functionality without requiring additional components.
2Reliability
If internal test circuits are added to the memory for performance testing, then the ability to test memory cell performance is improved, but the overall memory performance deteriorates
Solution Approach 1:
The patent implements dynamic mode switching between normal operation and test mode. The memory system can adaptively change its functionality based on control signals, allowing performance testing to be conducted without permanently degrading the memory's operational performance. The test circuitry is activated only when needed and does not interfere with normal memory operations.
Solution Approach 2:
The patent employs periodic test cycles where the memory operates in normal mode during most time and switches to test mode periodically for performance evaluation. This periodic activation of test functionality ensures that memory performance is assessed at intervals without continuously degrading the memory's productive capacity.
3Reliability
If the looped chain of test cells is continuously active, then performance testing can be performed, but energy consumption increases
Solution Approach 1:
The patent implements periodic activation of the test cell looped chain rather than continuous operation. The test mode is activated only when performance testing is required, and the system returns to normal operation mode otherwise. This periodic action significantly reduces energy consumption compared to continuous test mode operation.
Solution Approach 2:
The patent uses dynamic control of the test cell looped chain, switching between active test mode and inactive normal mode based on testing requirements. The control circuitry dynamically adjusts the state of test cells and associated transistors to minimize energy consumption during non-testing periods while maintaining testing capability when needed.
Data Source
AI summary
A memory includes a plurality of memory cells each including a true data input connected to a true bit line and complementary data input connected to a complementary bit line, and two inverters connected head-to-tail firstly to the true data input and secondly to the complementary data input. The memory also includes a test circuit includes a plurality of test cells, each test cell includes a true data input connected to a complementary data input of the preceding test cell and a complementary data input connected to the true data input of the following test cell, the complementary data input of the last test cell being connected to the true data input of the first test cell, each test cell comprising a first inverter connected between the true data input and the complementary data input. The looped chain thus formed propagates a signal whose period is a function of the performance of the storage cells.