Memory Test Mode Circuit for High-Speed Write Data Testing
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Solution Overview
Problem
Current DRAM and SDRAM technologies face challenges in testing high-speed graphics memory due to smaller signal amplitudes and data valid windows, leading to increased test system costs and degraded signal quality, making existing test solutions ineffective for delivering signals correctly into memory arrays.
Innovation Solution
A test mode circuit is implemented that allows write data to be tested at full system speed without changing the system clock frequency, using reduced signal integrity requirements, enabling write data testing within the memory array without external system input, and utilizing a test mode control signal to configure the I/O circuit for high-speed data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed writing test mode is implemented for memories, then writing speed is improved, but signal integrity deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-loading test data into an internal buffer before the actual write operation. This allows the memory system to prepare test patterns in advance, enabling full-speed writing without requiring external test equipment to deliver signals during the critical write window, thereby maintaining signal integrity while achieving high writing speed
Solution Approach 2:
The patent introduces an intermediary internal buffer that decouples the test data generation from the write operation. This buffer serves as a mediator between the test logic and the memory array, allowing data to be written at full system speed without requiring external test equipment to maintain signal integrity at high speeds
2Area of stationary object
If narrower memory bus width is used, then chip size is reduced, but test system cost increases
Solution Approach 1:
The patent applies self-service by implementing an internal test mode that generates and writes test data using the memory system's own resources. The internal buffer and test logic operate autonomously without requiring external test equipment, thereby reducing test system cost while maintaining the narrow chip footprint
Solution Approach 2:
The patent extracts the test function from external test equipment and relocates it within the memory device itself. By implementing internal test data generation and writing capability, the system eliminates the need for complex external test systems, reducing overall test system cost while maintaining compact chip size
3Speed
If smaller data valid window is used, then I/O speed is increased, but measurement precision deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-loading test data into the internal buffer before the data valid window occurs. This allows the system to have test data ready in advance, enabling precise measurement within the narrow data valid window while maintaining high I/O speed
Solution Approach 2:
The patent transitions from external test signal delivery to internal buffer-based test data provision. This dimensional shift from external timing-critical signal delivery to internal pre-prepared data allows the system to maintain measurement precision despite the narrow data valid window at high I/O speeds
Data Source
AI summary
Apparatuses and methods are provided for a high speed writing test mode for memories. An example apparatus includes a memory core, a data terminal coupled to a data receiver, a read buffer coupled between the data terminal and the memory core, and a write buffer coupled between the data receiver and the memory core. The write buffer may include at least a first input coupled to the data receiver, and a second input. While in a test mode, the write buffer may be loaded with data from the second input instead of the first input.