Memory Test Mode Using External Clock for Leakage Detection
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Solution Overview
Problem
Existing flash memory devices face challenges in accurately detecting defects due to the masking of leakage currents by relatively large external currents consumed by operational components, making it difficult to identify defects in the control logic circuit.
Innovation Solution
A memory device and test method that enables a test mode where components of the reference generating circuit are disabled, using an external clock signal and power to reduce current consumption, allowing for easier detection of leakage currents in the control logic circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the reference generating circuit operates normally to generate operating voltages and internal clock signal, then the memory device can perform normal operations, but the external current consumption increases which masks leakage currents and reduces defect detection accuracy
Solution Approach 1:
The patent extracts and disables specific components of the reference generating circuit (such as the internal clock signal generator and operating voltage generators) during test mode. By removing these components from operation, the external current consumption is reduced, allowing leakage currents in the control logic circuit to be detected without being masked by the larger operational current draw.
Solution Approach 2:
The patent implements dynamic configuration of the reference generating circuit, allowing it to switch between different operational states: normal mode where all components operate, and test mode where specific components are disabled. This dynamic adjustment enables the system to optimize current consumption based on the operational context, improving defect detection accuracy when needed.
2Measurement precision
If all components of the reference generating circuit are enabled, then complete functionality is maintained, but leakage current detection in the control logic circuit becomes difficult due to masking by larger external currents
Solution Approach 1:
The patent segments the reference generating circuit into distinct functional components: the internal clock signal generator, operating voltage generators, and the power supply interface. By segmenting the circuit, the test mode can selectively disable only the clock and voltage generation components while maintaining the power supply connection, thereby reducing current consumption without requiring complete circuit disassembly or complex reconfiguration.
3Measurement precision
If the memory device uses internal clock signal and internally generated operating voltages, then autonomous operation is achieved, but test accuracy is reduced due to high current consumption masking leakage currents
Solution Approach 1:
The patent prepares the memory device for test mode by pre-configuring the test mode circuit to recognize specific command signals. When a test command is received, the circuit automatically transitions to test mode, disabling the internal clock and voltage generation components before the actual defect detection begins. This preliminary configuration ensures that the device is ready for accurate leakage current measurement without requiring complex manual intervention during the test execution.
Data Source
AI summary
A memory device includes a memory cell array, a reference generating circuit, a row decoding circuit that is connected to the memory cell array through word lines, a page buffer circuit that is connected to the memory cell array through bit lines, a data input/output circuit that is connected to the page buffer circuit through a data line, a buffer circuit, a control logic circuit that performs logic sequences, based on the internal clock signal and the internal power, and a test mode circuit. When the memory device enters a test mode, the test mode circuit disables a part of components of the reference generating circuit. In the test mode, the control logic circuit performs the logic sequences by using an external clock signal provided from an external device.