Integrated Circuit Memory Test Module System
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Solution Overview
Problem
Existing memory testing techniques for integrated circuits are complex and inflexible, requiring knowledge of the physical layout of memory units, leading to increased costs and inefficiencies as the number of memory units grows, and necessitating rewritten test programs for layout changes.
Innovation Solution
An integrated circuit with a memory test module system that uses a transaction interface with address encodings for individual and group memory unit identification, allowing decode circuitry to perform register access operations without knowing the exact layout, enabling flexible and efficient testing of memory units without requiring specific knowledge of their location.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate BIST mechanism is provided for each embedded memory, then testing reliability is improved, but chip area increases unacceptably
Solution Approach 1:
The patent merges multiple separate BIST mechanisms into a single shared BIST mechanism that can service multiple embedded memory blocks. This is achieved through a centralized test controller that coordinates testing across all memory blocks, sharing common test logic, pattern generation, and result analysis resources, thereby reducing the total chip area dedicated to testing while maintaining comprehensive test coverage
Solution Approach 2:
The shared BIST mechanism is designed with universal functionality to handle multiple different types of embedded memory blocks. The test controller can dynamically configure and adapt its testing approach for each memory block, making a single mechanism capable of performing the roles that would otherwise require multiple specialized mechanisms, thus reducing area while preserving testing reliability
2Area of stationary object
If a single shared BIST mechanism is provided for multiple embedded memories, then chip area is reduced, but test complexity increases
Solution Approach 1:
The patent segments the testing process into distinct phases and functional components that can be independently managed. The test controller divides memory blocks into groups that can be tested separately, and implements a systematic approach where test patterns are generated, applied, and analyzed in discrete steps. This segmentation reduces the perceived complexity by breaking down the monolithic shared BIST mechanism into manageable, modular functional units
Solution Approach 2:
The patent introduces intermediary components such as test interfaces and control logic that mediate between the shared BIST mechanism and individual memory blocks. These intermediaries simplify the interaction complexity by providing standardized communication protocols and abstraction layers, allowing the shared BIST mechanism to manage multiple memory blocks without direct complex point-to-point connections
3Ease of manufacture
If traditional test vector style testing is used, then manufacturing cost is reduced for small memory areas, but testing time grows exponentially with memory die area
Solution Approach 1:
The patent implements periodic action through algorithmic test patterns that systematically cycle through memory addresses and data values. Instead of using exhaustive traditional test vectors, the BIST mechanism employs repeating test algorithms (such as march tests) that periodically access different memory locations with structured patterns, achieving comprehensive coverage in logarithmic time rather than exponential time relative to memory size
Solution Approach 2:
The patent enables self-service through the Built-In Self-Test capability where the memory system tests itself using on-chip resources. The BIST mechanism generates its own test patterns, applies them to the memory blocks, captures the responses, and analyzes the results autonomously without requiring external test equipment to generate and apply complex test vectors, thereby dramatically reducing testing time while maintaining manufacturing cost effectiveness
4Ease of manufacture
If traditional test vector style testing is used, then simple test equipment is sufficient, but it is not possible to detect all possible types of memory defect
Solution Approach 1:
The patent employs parameter changes through algorithmic test patterns that systematically vary test parameters such as address sequences, data values, and timing relationships. The BIST mechanism dynamically changes these parameters during testing to stress different aspects of memory operation, enabling detection of various defect types (such as coupling defects, retention defects, and access defects) that static traditional test vectors cannot detect, while still using simple on-chip test equipment
Data Source
AI summary
An integrated circuit includes memory units and at least one memory test module, each module includes one associated memory unit, a set of test registers therefor, and a test engine configured to perform a test operation on that associated memory unit. A transaction interface of the memory test module receives a transaction specifying a register access operation and providing a first address portion having encodings allowing individual memory units as well as groups of memory units to be identified, and a second address portion identifying one of the test registers within the set to be an accessed register. Decode circuitry, within each memory test module and responsive to the transaction, is configured to selectively perform the register access operation if it is determined that the memory test module includes a set of test registers associated with a memory unit.