Semiconductor Memory Device Test Pad Current Mirror Circuit
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Solution Overview
Problem
Conventional semiconductor memory devices with Floating Body Cells (FBCs) face challenges in simultaneously testing all memory cells due to variations in threshold voltage, requiring individual testing of each bit, leading to lengthy measurement times as the number of memory cells increases.
Innovation Solution
A semiconductor memory device design incorporating a memory cell array with word lines, bit lines, sense amplifiers, and test circuits that utilize a current mirror circuit and transfer gates to pass reference currents and voltages, allowing simultaneous testing of all memory cells connected to a common test pad, reducing the need for individual bit testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If individual testing of each memory cell is performed due to threshold voltage variations, then measurement precision is maintained, but measurement time increases significantly
Solution Approach 1:
The patent merges multiple individual memory cell tests into a single group test by connecting multiple memory cells to a common test pad through bit lines. The current mirror circuit enables simultaneous measurement of multiple cells' threshold voltages by replicating the reference current to multiple test circuits, thereby maintaining measurement precision while significantly reducing the time required to test all memory cells in the array.
Solution Approach 2:
The test circuit is designed with multi-functionality to handle both individual and group testing modes. The current mirror circuit can distribute the reference current to multiple test circuits simultaneously, allowing the same test pad and basic test circuitry to serve multiple memory cells. This universal design enables the system to maintain precise threshold voltage measurement capability while scaling to test large numbers of memory cells efficiently.
2Device complexity
If a common test pad is used for multiple memory cells, then device complexity is reduced, but measurement precision may deteriorate due to current distribution issues
Solution Approach 1:
The current mirror circuit acts as an intermediary between the single test pad and multiple memory cells. It receives a reference current from the test pad and precisely replicates and distributes this current to multiple test circuits through bit lines. This intermediary mechanism ensures that each memory cell receives an accurate and consistent test current, maintaining measurement precision while allowing multiple cells to share a common test pad interface.
Solution Approach 2:
The patent utilizes parameter changes in the current mirror circuit to maintain precision across multiple cells. By adjusting the mirror ratio and controlling the reference current magnitude, the system can optimize the test current distribution to match the specific characteristics of different memory cells. This parameter adjustment capability ensures that measurement precision is maintained even when testing multiple cells with varying threshold voltages through a common test pad.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables high-speed testing of memory cells by using a common test pad and current mirror circuit, significantly reducing the overall test time and improving efficiency as the number of memory cells increases.
Implementation Method 1
test circuits connected between the power source and the test pad and intervening between the power source and the bit lines, the test circuits passing test currents according to the reference voltage via the bit lines
Implementation Method 2
sense amplifiers connected to the bit lines, and detecting data stored in the memory cells
Data Source
AI summary
This disclosure concerns a semiconductor memory device comprising: a memory cell array having memory cells arrayed two-dimensionally; word lines connected to the memory cells of rows of the memory cell array; bit lines connected to the memory cells of columns of the memory cell array; sense amplifiers connected to the bit lines, and detecting data stored in the memory cells; a test pad passing a predetermined reference current from a power source, and transmitting a reference voltage based on the reference current; and test circuits connected between the power source and the test pad and intervening between the power source and the bit lines, the test circuits passing test currents according to the reference voltage via the bit lines.