Memory Test Path Bypassing Cells for Peripheral Circuit Verification
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Solution Overview
Problem
Current memory devices lack comprehensive testing capabilities for their analog hard-macro portions, particularly for peripheral components, which are crucial for assessing read performance, driver strengths, and detecting process-related defects.
Innovation Solution
The memory device operates in a test mode where both the read and write circuits are utilized to test each other, bypassing the memory cells. This allows for the emulation of cell currents with minimal analog resources and stimulates all states with minimal overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells are used for testing, then test coverage is improved, but memory cell wear and potential damage occur
Solution Approach 1:
The patent extracts the testing function from the memory cells themselves by providing alternative test paths that bypass the memory cells. Test data is written to and read from buffer memory instead, allowing comprehensive testing of read/write circuits without subjecting the actual memory cells to wear-inducing test operations.
Solution Approach 2:
The patent introduces buffer memory as an intermediary component between the test circuits and the memory cells. This intermediary allows test operations to be performed on the buffer memory while the memory cells remain protected, serving as a mediator that enables testing without direct interaction between test signals and memory cells.
2Reliability
If additional test circuits are added, then testing capability is improved, but device complexity and area increase
Solution Approach 1:
The patent makes existing buffer memory serve multiple functions: it acts as both operational buffer memory during normal device operation and as test memory during testing operations. This multi-functionality eliminates the need for separate dedicated test memory structures, reducing overall device complexity while maintaining comprehensive testing capability.
Solution Approach 2:
The patent merges the test memory function with the existing buffer memory structure. By combining these functions into a single component, the patent avoids duplicating circuitry and reduces the overall complexity of the device while enabling comprehensive testing of read/write circuits.
3Measurement precision
If comprehensive testing of peripheral components is performed, then defect detection is improved, but test time and overhead increase
Solution Approach 1:
The patent enables continuous testing of read/write circuits through the buffer memory without interruption to normal operations. The buffer memory can be tested while maintaining system functionality, allowing testing to occur continuously rather than requiring separate dedicated test periods, thereby reducing overall test time overhead.
Data Source
AI summary
A memory device is provided. The memory device comprises at least one non-volatile memory cell, a write circuit configured to write to the at least one memory cell, and a read circuit configured to read from the at least one memory cell, wherein the memory device is configured to be operable in a test operating mode, in which at least one test path can be tested, and wherein the test path comprises at least a portion of the write circuit and at least a portion of the read circuit, and bypasses the at least one memory cell.