Memory Test and Repair Using Redundant Portions
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Solution Overview
Problem
The increasing memory density in integrated circuits leads to lower memory yield and longer memory test times, as the number of bits on a chip increases, making it challenging to effectively test and repair memory failures within the ICs.
Innovation Solution
The integration of a memory module with a memory array comprising a first memory portion and a redundant memory portion, a failed memory indicator, and a wrapper circuit that uses the redundant portion to repair the memory array upon detection of a failed portion, along with a module control circuit for performing built-in self-tests and broadcasting configurations for memory testing and repair.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory density is increased to improve storage capacity, then memory yield decreases and test time increases
Solution Approach 1:
The patent applies preliminary action by performing built-in self-tests during the manufacturing process to identify and isolate failed memory portions before the IC is delivered to the customer. The wrapper circuit proactively detects failures and activates redundant memory portions in advance, preventing yield loss from undetected defects.
Solution Approach 2:
The patent implements beforehand cushioning by incorporating redundant memory portions alongside the main memory array during fabrication. These redundant portions serve as a buffer against failures, allowing the system to compensate for defective memory cells without requiring complete chip replacement, thus maintaining yield despite increased density.
2Quantity of substance
If memory density is increased to improve storage capacity, then test time increases
Solution Approach 1:
The patent applies segmentation by dividing the memory array into multiple independently testable blocks, each with its own wrapper circuit. This allows parallel testing of different memory segments simultaneously, reducing total test time while maintaining comprehensive coverage of the high-density memory structure.
Solution Approach 2:
The patent implements self-service through built-in self-test (BIST) functionality embedded within the memory structure itself. The memory blocks can perform self-diagnosis and self-repair operations without requiring external test equipment, significantly reducing the time needed for production testing and validation.
3Ease of repair
If redundant memory portion is added to enable repair functionality, then device complexity increases
Solution Approach 1:
The patent applies universality by designing the wrapper circuit to perform multiple functions: it monitors memory health during normal operation, executes self-tests, identifies failed portions, and manages redundancy activation. This multi-functional approach consolidates complexity into a single control structure rather than requiring separate dedicated circuits for each function.
Solution Approach 2:
The patent implements the nested doll principle by placing the wrapper circuit within the memory block structure itself, nesting the control and monitoring functionality inside the memory array. The redundant memory portions are integrated alongside the main array during fabrication, creating a compact nested structure that minimizes overall complexity while enabling repair capabilities.
Data Source
AI summary
Aspects of the disclosure provide an integrated circuit (IC) chip. The IC chip includes a memory module that includes one or more memory blocks. Each memory block includes a memory array having a first memory portion and a redundant memory portion, a failed memory indicator that, in response to a memory test, is configured to provide an indication of a failed memory portion in the first memory portion, and a wrapper circuit that, in response to the indication of the failed memory portion, is configured to repair the memory array by using the redundant portion instead of the failed memory portion.