Semiconductor Memory Test Circuit Segmentation
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Solution Overview
Problem
The increasing integration and capacity of semiconductor memory apparatuses complicate the fabrication process and test methods, particularly in detecting defective cells, due to the large number of test target memory cells per wafer or packaged chip.
Innovation Solution
A semiconductor memory apparatus and test method that include a read/write circuit unit, internal voltage generator, and controller, which generate internal voltages and pre-read signals during a test mode, allowing for comparison of data from memory cells and selective driving of write circuits based on the comparison results, enabling efficient detection and writing of test data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the integration degree and capacity of semiconductor memory apparatuses are increased, then the storage capacity and functionality are improved, but the fabrication process complexity and test difficulty increase
Solution Approach 1:
The memory apparatus is divided into multiple memory cell arrays (first memory cell array and second memory cell array) with separate read/write circuit units. This segmentation allows independent testing and operation of different memory regions, reducing the overall test complexity while maintaining high storage capacity.
2Quantity of substance
If the integration degree and capacity of semiconductor memory apparatuses are increased, then the storage capacity is improved, but the test process complexity increases
Solution Approach 1:
A voltage generation circuit generates required internal voltages (such as read voltage and write voltage) in advance before actual memory operations. This preliminary voltage preparation simplifies the test process by ensuring all necessary voltage conditions are ready, reducing test setup complexity for high-capacity memory arrays.
Solution Approach 2:
A controller acts as an intermediary between external test equipment and the memory cell arrays, managing test operations, voltage generation, and data reading. This intermediary structure simplifies the test process by providing a centralized control interface, making it easier to test high-capacity memory apparatuses without proportionally increasing test complexity.
3Measurement precision
If the number of test target memory cells per wafer or per packaged chip is increased, then the test coverage is improved, but the test time and processing duration increase
Solution Approach 1:
Multiple memory cell arrays are tested independently through separate read/write circuit units, allowing parallel test operations. This segmentation enables comprehensive test coverage of all memory cells while reducing total test time by conducting tests simultaneously across different memory regions.
Solution Approach 2:
The voltage generation circuit continuously maintains required internal voltages during test operations, eliminating voltage setup delays between test cycles. This continuous voltage supply enables uninterrupted testing across all memory cell arrays, improving test efficiency and reducing overall test time while maintaining complete test coverage.
Data Source
AI summary
A semiconductor memory apparatus may include a read/write circuit unit configured to receive an external voltage, to read data from a memory cell array, and to generate a pre-read signal, while an internal voltage is generated during a test mode, and a controller configured to selectively drive a write circuit unit in response to the pre-read signal.