Dynamic Memory Test Strategy Selection

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Solution Overview

Problem

Current memory test systems lack efficient methods for testing memories during production, leading to high fault and defective rates, necessitating the development of a more effective memory test system and method.

Innovation Solution

A memory test system comprising test devices connected to a host computer via driving modules, which allows for data interaction and control, using preset or initial test strategies to obtain test results, and dynamically adjusts test strategies based on the memory faults detected.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional memory test methods are used during production, then the testing process is simple, but the fault rate and defective rate are high

Engineering Contradiction:
Improvememory fault rateVSAvoidtest efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements dynamic test strategy selection where the system automatically chooses between preset test strategies and initial test strategies based on real-time detection needs. The test device dynamically adjusts testing parameters and methods during the production process, allowing flexible adaptation to different memory types and fault patterns while maintaining high test efficiency.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system incorporates feedback mechanisms where test results are analyzed in real-time and used to adjust subsequent testing parameters. The control device receives test data, compares it against criteria, and dynamically modifies test strategies based on detected patterns, improving both reliability and efficiency through continuous optimization.

Inventive Principle:
Principle #23Feedback

2Reliability

If comprehensive memory testing is performed to reduce defective rates, then the test coverage increases, but the testing time and complexity increase

Engineering Contradiction:
Improvedefective rateVSAvoidtesting time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs preliminary classification of memory devices based on initial quick tests, then applies targeted comprehensive testing only to devices that require it. Preset test strategies are prepared in advance based on historical data and memory specifications, enabling rapid execution of comprehensive tests when needed without increasing overall testing time for all devices.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If multiple test strategies are used to improve test accuracy, then the test precision increases, but the system complexity increases

Engineering Contradiction:
Improvetest accuracyVSAvoidsystem complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent divides test strategies into distinct preset strategies and initial strategies, each optimized for specific testing scenarios. The control device segments the decision-making process into clear conditional branches, selecting appropriate test strategies based on device characteristics and test requirements, thereby managing complexity through structured organization of multiple test methods.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11862278B2Memory test systems and memory test methods
Publication Date: 2024.01.02 CHANGXIN MEMORY TECH INC
  • US11862278B2 patent drawing
  • US11862278B2 patent drawing
  • US11862278B2 patent drawing

AI summary

The present disclosure relates to a memory test system and a memory test method. The memory test system comprises: a plurality of test devices, a host computer, and driving modules. Each of the test devices is provided with a test interface used for connecting a memory to be tested. The host computer is respectively connected to the plurality of test devices and configured to control the test devices to test the memory to be tested. The driving modules are connected to the test devices and configured to output, to the test devices, driving signals used for driving the test devices to perform data interaction with the host computer.