Memory Test Circuit Using THV Time-Multiplexed State Signals
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Solution Overview
Problem
The increasing integration and miniaturization of semiconductor memory devices lead to a limitation in the number of Through Hole Vias (THVs) available for testing, necessitating adjustments in the number of THVs for power and signal supply, which complicates the testing process.
Innovation Solution
A semiconductor memory device design that includes a state machine, logical sum calculator, and accumulation circuit to reduce the number of probing pads and THVs required for testing, utilizing a toggle signal to efficiently manage clock signals and output to probing pads through THVs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of Through Hole Vias (THVs) is increased to supply power and operating signals for higher integration, then the degree of integration is improved, but the number of available THVs for testing is reduced
Solution Approach 1:
The state machine outputs state signals through multiple output terminals that can be selectively activated. The accumulation circuit with toggle signal enables a single probing pad to sequentially receive multiple state signals over time, allowing one THV to serve multiple testing functions that would traditionally require multiple separate testing paths.
Solution Approach 2:
The patent transitions from spatial multiplexing (multiple probing pads connected to multiple THVs) to temporal multiplexing (single probing pad receiving multiple state signals at different times). The accumulation circuit accumulates state signals over time and outputs them sequentially through a single THV, adding a time dimension to the testing architecture.
2Measurement precision
If the number of probing pads is increased to test multiple state signals simultaneously, then the testing completeness is improved, but the number of required Through Hole Vias increases
Solution Approach 1:
The patent converts a spatial problem (multiple probing pads required for simultaneous testing) into a temporal solution (sequential testing over time). The accumulation circuit receives multiple state signals from different output terminals of the state machine and outputs them sequentially through a single probing pad, eliminating the need for multiple THVs while maintaining testing completeness.
Solution Approach 2:
The accumulation circuit dynamically activates different output terminals of the state machine at different times based on the testing sequence. The toggle signal enables time-multiplexed access to multiple state signals through a single probing pad, making the testing architecture dynamic rather than static.
Data Source
AI summary
A semiconductor memory device is provided, comprising: a memory cell region including a memory cell array; and a peripheral circuit region which at least partially overlaps the memory cell region and includes control logic configured to control operation of the memory cell array, wherein the control logic includes a state machine configured to output a plurality of state signals responsive to operation commands of the memory cell region, the plurality of state signals including a first state signal output from a first output terminal, and a second state signal output from a second output terminal different from the first output terminal, a logical sum calculator configured to perform a logical sum calculation based on at least one of the first state signal or the second state signal, and an accumulation circuit configured to receive an output of the logical sum calculator as a clock signal, and that outputs a toggle signal to one probing pad in response to the clock signal, the accumulation circuit being connected to the probing pad through a Through Hole Via (THV) penetrating the memory cell region.