Memory Test Device Voltage Adjustment Method

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Solution Overview

Problem

Conventional methods for testing the impact of voltage variations on dynamic random access memory (DRAM) are time-consuming and inefficient, requiring extensive manual intervention and unable to interrupt testing without affecting results, which hinders quick verification and analysis during the early stages of product development.

Innovation Solution

A test device and method that systematically adjusts core and peripheral voltages of a memory device through a series of voltage steps, allowing for rapid testing under low-voltage, normal-voltage, and high-voltage conditions using a controller to access and read the memory device, generating test results that can be analyzed efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional test methods are used to verify voltage impact on DRAM, then test results can be obtained, but verification time is extremely long and analysis efficiency is low

Engineering Contradiction:
Improveverification timeVSAvoidtest time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent applies parameter changes by systematically varying core voltage and peripheral voltage across multiple test steps. The controller adjusts voltage parameters to different levels (e.g., first voltage value, second voltage value, third voltage value, fourth voltage value) to evaluate memory device performance under various voltage conditions, enabling efficient verification of voltage impact without time-consuming manual testing

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The test device performs self-service through automated voltage adjustment and testing. The controller automatically sets core and peripheral voltages to predetermined values, executes read and write operations, and collects test results without requiring manual intervention, thereby significantly reducing verification time and improving analysis efficiency

Inventive Principle:
Principle #25Self-service

2Extent of automation

If manual testing operations are performed, then test results can be analyzed, but test operation cannot be interrupted and requires extensive analyst time

Engineering Contradiction:
Improvetest operation automationVSAvoidmanual intervention requirement
Core Design Contradiction:
Extent of automationVSEase of operation

Solution Approach 1:

The test device implements self-service by enabling the controller to automatically adjust core and peripheral voltages to predetermined values, execute memory read and write operations, and collect test results without manual intervention. This automation eliminates the need for extensive analyst time while maintaining comprehensive testing capability

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system incorporates feedback mechanisms where the controller monitors test results from memory read operations and uses this information to evaluate voltage impact. The feedback loop enables automated analysis and comparison of performance under different voltage conditions, reducing the need for manual intervention in the testing process

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12154644B2Test device and test method thereof
Publication Date: 2024.11.26 NAN YA TECH
  • US12154644B2 patent drawing
  • US12154644B2 patent drawing
  • US12154644B2 patent drawing

AI summary

A test device method includes: setting a core voltage of a memory device to a first voltage value and a peripheral voltage of the memory device to a second voltage value; testing the memory device by accessing the memory device based on the core voltage and the at least one peripheral voltage; adjusting the core voltage to a third voltage value and the at least one peripheral voltage of the memory device to a fourth voltage value; testing the memory device by reading the memory device based on the core voltage and the at least one peripheral voltage; adjusting the core voltage to a fifth voltage value and the at least one peripheral voltage of the memory device to a sixth voltage value; and testing the memory device by reading the memory device based on the core voltage and the at least one peripheral voltage.