Memory Device Self-Test Iterative Write Failure Detection
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Solution Overview
Problem
Existing memory device testing methods fail to accurately detect write failures in semiconductor memory devices, leading to unexpected failures when the devices are used, as stochastic write failures may not be detected during testing.
Innovation Solution
A test method involving iterative pattern write operations, where failure information is written in memory cells with write failures, allowing for improved detection of failure cells by skipping re-write operations for identified failure cells, thereby enhancing the accuracy of failure detection and device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single pattern write operation is performed during testing, then the test process is simple and fast, but write failures may not be detected due to stochastic occurrence
Solution Approach 1:
The test method performs multiple iterative pattern write operations on the memory device. Each iteration writes a test pattern and reads back the data to check for write failures. This periodic repetition increases the probability of detecting stochastic write failures that may not occur in a single test operation, thereby improving reliability without requiring complex test equipment
Solution Approach 2:
The test method uses feedback by reading back the data after each pattern write operation and comparing it with the expected test pattern. When a write failure is detected, the test controller records the failed address and adjusts subsequent test patterns to target previously failed addresses, improving detection accuracy through iterative feedback
2Measurement precision
If multiple iterative pattern write operations are performed to detect write failures, then detection accuracy improves, but test time increases
Solution Approach 1:
The test method extracts and isolates only the addresses that exhibit write failures from the entire memory address space. By focusing subsequent test operations only on these failed addresses rather than testing all addresses repeatedly, the method significantly reduces test time while maintaining high detection accuracy for problematic cells
Solution Approach 2:
The test method performs partial testing by concentrating test efforts on specific failed addresses identified in previous iterations rather than uniformly testing all memory addresses. This partial action approach achieves sufficient detection precision for critical failures without the time cost of exhaustive testing
Data Source
AI summary
A test method for a memory device including a plurality of memory cells includes generating a first test pattern, performing a first pattern write operation of writing the first test pattern in the plurality of memory cells, reading first data from the plurality of memory cells in which the first test pattern was written, generating a second test pattern based on the first data, and performing a second pattern write operation of writing the second test pattern in the plurality of memory cells. The second test pattern is generated such that a write operation is skipped with regard to failure cells from among the plurality of memory cells at which a write failure occurs, during the second pattern write operation.