Memory Tester Don't Care Bit Handling via Mask Data
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory testers face challenges in effectively testing semiconductor devices, such as NAND type flash memories, due to limitations in handling and interpreting scan input data with don't care bits, which affect the accuracy of test results.
Innovation Solution
A memory tester configuration that includes a first memory for storing scan input data and expected value data, a second memory for storing scan output data and mask data, and an arithmetic circuit performing an exclusive or operation between the expected value data and scan output data, with a determination circuit to assess the don't care bit's pass or fail status using mask data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing memory testers use conventional scan testing methods, then the testing process is simple, but the accuracy of test results is reduced due to inability to properly handle don't care bits
Solution Approach 1:
The patent segments the test data into two distinct parts: scan input data containing don't care bits and scan output data. It also separates the processing logic by introducing mask data that corresponds to the don't care bit positions. This segmentation allows the system to handle don't care bits specially while maintaining overall test accuracy, resolving the contradiction between precision and complexity.
Solution Approach 2:
The patent introduces mask data as an intermediary element between the scan input data and the comparison result. The mask data serves as a mediator that identifies which bits are don't care bits, allowing the determination circuit to ignore those positions during comparison. This intermediary mechanism enables accurate testing without requiring complex modifications to the basic test structure.
2Reliability
If the memory tester handles don't care bits, then the test coverage is improved, but the determination of pass/fail status becomes more complex
Solution Approach 1:
The patent extracts the don't care bit information from the scan input data and represents it separately through mask data. By taking out the don't care bit handling logic into a separate mask data structure, the system can maintain comprehensive test coverage while simplifying the pass/fail determination process. The determination circuit only needs to compare bits where mask data indicates they are not don't care bits.
3Measurement precision
If the memory tester uses conventional comparison methods, then the operation is simple, but the test accuracy is reduced due to inability to isolate don't care bits
Solution Approach 1:
The patent applies local quality by treating different bits differently based on their nature. Through mask data, the system identifies which bits are don't care bits and applies special handling only to those positions. This allows accurate comparison at non-don't care positions while maintaining simplicity in the overall processing structure, as the same comparison logic is used throughout, just with selective application.
Data Source
AI summary
A memory tester of the present embodiment includes a first memory, a second memory, an arithmetic circuit, and a determination circuit. The first memory is configured to store scan input data and expected value data, the scan input data including a don't care bit, the expected value data being obtained by converting the don't care bit into a first predetermined value. The second memory is configured to store scan output data and mask data obtained by converting a value of the scan input data other than the don't care bit into a second predetermined value. The arithmetic circuit is configured to perform an exclusive or operation between the expected value data and the scan output data. The determination circuit is configured to determine whether the don't care bit of an arithmetic result from the arithmetic circuit is passed or failed by using the mask data.