Memory Testing Software Verification via Simulated BIST Fails
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Solution Overview
Problem
Current methods for verifying the accuracy of logical-to-physical mapping software in memory testing are inadequate, prone to errors due to miscommunication of algorithms and unaccounted cycle delays, leading to uncertainty in identifying physical defects.
Innovation Solution
A built-in self-test (BIST) fail control function generates simulated memory fails at predetermined locations within a memory array, allowing for the verification of logical-to-physical mapping software by comparing generated bit fail maps with known simulated fail locations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If physical observation methods are used to verify logical-to-physical mapping software, then reliability of defect identification is improved, but device complexity and cost increase
Solution Approach 1:
The patent creates a virtual copy of the memory device with simulated defects that mirror the logical-to-physical mapping process. This virtual model allows verification of the mapping software without physical observation, reducing complexity while maintaining reliability through controlled simulation of known defect scenarios
Solution Approach 2:
The patent introduces an intermediary simulation layer between the logical-to-physical mapping software and physical observation. This intermediary generates virtual defect data that can be processed by the mapping software, allowing verification without direct physical observation and reducing the complexity of the verification process
2Measurement precision
If physical stripping and observation of memory devices is performed, then measurement precision of defect locations is improved, but loss of time and productivity decrease
Solution Approach 1:
The patent performs preliminary actions by pre-configuring simulated defects in the virtual memory model before running the logical-to-physical mapping software. This allows the mapping software to be verified with known defect locations already established, eliminating the need for time-consuming physical stripping and observation while maintaining precision through controlled simulation
Solution Approach 2:
The patent creates virtual copies of defect scenarios that can be rapidly instantiated and tested, replacing the time-consuming physical process of creating and observing actual defects. This virtual copying maintains measurement precision through exact replication of defect conditions while dramatically reducing the time required for verification
3Reliability
If multiple physical defects are observed with high accuracy, then reliability of mapping software verification is improved, but ease of manufacture and cost worsen
Solution Approach 1:
The patent replaces expensive and complex physical defect observation with virtual defect simulation. The virtual model allows multiple defect scenarios to be created and tested digitally, maintaining reliability through controlled simulation while dramatically improving ease of manufacture and reducing costs by eliminating physical device stripping and observation requirements
Solution Approach 2:
The patent implements a self-service verification system where the virtual memory model automatically generates defect data and enables the mapping software to verify itself without requiring external physical observation. This self-service approach maintains reliability through automated controlled testing while improving ease of manufacture by eliminating the need for specialized failure analysis facilities and procedures
Data Source
AI summary
A method for verifying the accuracy of memory testing software is disclosed. A built-in self test (BIST) fail control function is utilized to generate multiple simulated memory fails at various predetermined locations within a memory array of a memory device. The memory array is then tested by a memory tester. Afterwards, a bit fail map is generated by the logical-to-physical mapping software based on all the memory fails indicated by the memory tester. The bit fail map provides all the fail memory locations derived by the logical-to-physical mapping software. The fail memory locations derived by the logical-to-physical mapping software are then compared to the predetermined memory locations to verify the accuracy of the logical-to-physical mapping software.