Memory Testing Circuit with Built-In Self-Test for Fault Localization
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Solution Overview
Problem
Current memory test solutions require multiple logic circuits and decoding circuits to locate faulty memory cells, leading to circuit delay, increased circuit area, and higher testing costs.
Innovation Solution
A memory device and testing method that includes a pattern generating circuit, multiple memory modules, and a logic circuit. The pattern generating circuit generates test pattern data, a test address, and reference data, which the memory modules use for a built-in self-test (BIST). The logic circuit generates an indicator signal based on the test results, allowing the pattern generating circuit to retain the test address and perform a localization test to determine the faulty memory cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple logic circuits and decoding circuits are used to locate faulty memory cells, then the faulty memory cell can be located, but circuit delay increases and overall circuit area is increased
Solution Approach 1:
The memory device performs self-testing using built-in test circuits within each memory module. The pattern generating circuit generates test patterns that are applied to memory modules, which then self-test and generate test results without requiring external complex logic and decoding circuits. This self-service approach eliminates the need for additional external circuitry while maintaining the ability to locate faulty cells.
Solution Approach 2:
The testing function is segmented and distributed within each memory module itself. Each memory module contains its own test circuitry that can independently perform testing operations. This segmentation eliminates the need for a centralized complex testing system and reduces overall circuit area by distributing functionality where it is needed.
2Measurement precision
If multiple logic circuits and decoding circuits are used to locate faulty memory cells, then the faulty memory cell can be located, but significant circuit delay is introduced
Solution Approach 1:
By implementing self-testing within memory modules, the test operations are performed locally without requiring signals to traverse through multiple external logic and decoding circuits. This reduces the testing time and circuit delay significantly while maintaining the precision of faulty cell location.
Solution Approach 2:
The pattern generating circuit pre-generates test patterns and prepares test addresses before actual testing begins. This preliminary preparation eliminates the need for complex real-time decoding and processing during testing, thereby reducing circuit delay while maintaining accurate faulty cell location capability.
3Measurement precision
If multiple logic circuits and decoding circuits are used to locate faulty memory cells, then the faulty memory cell can be located, but memory testing costs are greatly increased
Solution Approach 1:
The memory device includes built-in test circuits that enable self-testing without requiring expensive external testing equipment. The pattern generating circuit and test circuits are integrated within the memory structure itself, eliminating the need for separate complex testing systems and significantly reducing manufacturing and testing costs while maintaining accurate faulty cell location.
Solution Approach 2:
The memory modules are designed with multi-functionality, serving both storage and self-testing functions. The same hardware structure performs both data storage and fault detection, eliminating the need for separate dedicated testing hardware and reducing overall system cost while maintaining testing precision.
Data Source
AI summary
A memory testing method includes the operations of: generating test pattern data, a test address and reference data by a pattern generating circuit; performing a built-in self-test (BIST) according to the test pattern, the test address and the reference data by multiple memory modules to generate multiple test results; generating an indicator signal according to the multiple test results; when a first test result among the multiple test results indicates a fault, retaining the test address by the pattern generating circuit in response to the indicator signal, and testing, according to the test address and multiple sets of predetermined pattern data, a first memory module among the multiple memory modules that corresponds to the first test result to generate a localization test result; and determining a faulty memory cell in the first memory module according to the localization test result.