Memory Testing Circuit for Leakage Detection
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Solution Overview
Problem
Uncontrollable factors during memory preparation, such as temperature and humidity issues, or shorting of Word Line (WL) and Bit Line (BL) signals, can cause leakage behavior between the WL and BL signal ends, preventing normal data writing and reading in memories, leading to operational harm.
Innovation Solution
A circuit with a switch control circuit is used to input a trigger signal, connecting between the discharge end and negative bias signal end of a Sub Wordline Drive (SWD), to detect potential leakage by ensuring the WL signal end meets a preset potential suspension range, determining if the stored signal level remains consistent with the initial level within a preset time, indicating leakage between the WL and BL signal ends.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional memory testing methods are used, then manufacturing process simplicity is maintained, but leakage behavior between WL and BL signal ends cannot be detected, leading to operational failures
Solution Approach 1:
The testing circuit performs preliminary detection of leakage behavior between WL and BL signal ends before memory operation. By initializing the to-be-tested circuit and applying test signals in advance, the system identifies potential leakage issues before they affect normal memory operations, thereby improving reliability without requiring complex operational testing during memory use.
Solution Approach 2:
A dedicated testing circuit acts as an intermediary between the memory circuit and the detection system. This separate testing circuit applies trigger signals to the WL signal end and monitors the BL signal end, isolating the detection function from the main memory operation circuitry. This approach enables reliable leakage detection while maintaining relatively simple overall system architecture.
2Measurement precision
If the WL signal end potential is not controlled within preset range, then circuit operation is simple, but leakage behavior cannot be accurately detected
Solution Approach 1:
The testing circuit controls the potential of the WL signal end within a preset range (between 0V and VDD) during the detection process. By adjusting and maintaining the WL signal end potential within this specific parameter range, the circuit creates optimal conditions for detecting leakage behavior. The switch control circuit modifies the potential state dynamically during testing, enabling precise leakage detection while keeping the control process manageable through automated signal management.
3Productivity
If memory units with leakage behavior are not identified, then all memory units can be used, but normal data writing and reading are prevented
Solution Approach 1:
The testing circuit extracts and identifies memory units exhibiting leakage behavior by monitoring the BL signal end for abnormal potential changes. Once leakage is detected in specific memory units, these faulty units are separated from the usable memory pool. This allows the system to continue operating with only the healthy memory units, maintaining productivity while ensuring data operation reliability by excluding defective units.
Data Source
AI summary
A circuit for testing a memory and a test method thereof are provided. According to the circuit for testing a memory provided by the present disclosure, a switch control circuit is connected between a discharge end and a negative bias signal end of a Sub Wordline Drive (SWD) and configured to input a trigger signal, so that potential of a Word Line (WL) signal end in a to-be-tested circuit meets a preset potential suspension range. Then, it is determined whether there is leakage behavior between the WL signal end and a Bit Line (BL) signal end in the to-be-tested circuit by detecting whether the present level state of a stored signal in the to-be-tested circuit is consistent with an initial level state. The to-be-tested circuit is a corresponding circuit in a single memory.