Memory Testing Clock Adjustment for Timing Slack Optimization
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Solution Overview
Problem
Existing memory-testing methods, such as Automatic Test Pattern Generation (ATPG), are inefficient and costly due to large test patterns and timing path discrepancies, leading to unreliable and inaccurate testing results, especially when the timing margin of the test mode exceeds that of the functional mode.
Innovation Solution
A memory-testing device and method that utilize a testing clock signal different from the original clock signal to adjust the timing slack, specifically by using a clock adjusting circuitry to generate a testing clock signal that reduces the timing margin of the test mode to be approximately equal to or smaller than that of the functional mode, thereby improving testing reliability and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a testing clock signal different from the original clock signal is used to adjust timing slack, then testing reliability and accuracy are improved, but device complexity increases due to additional clock adjusting circuitry
Solution Approach 1:
A clock adjusting circuitry is introduced as an intermediary component between the original clock signal source and the testing circuitry. This intermediary generates a testing clock signal with adjusted timing characteristics, allowing independent optimization of test timing without modifying the original system clock, thereby improving testing reliability while isolating the complexity to a dedicated adjustment module
Solution Approach 2:
The invention changes the timing parameters of the clock signal by introducing a testing clock signal with different timing characteristics than the original clock signal. This parameter change allows the timing slack to be optimized for testing operations independently, improving testing accuracy without affecting the functional mode timing
2Measurement precision
If ATPG testing method is used with critical path testing, then testing coverage is improved, but testing time and cost increase significantly due to large test pattern size
Solution Approach 1:
The invention extracts and focuses testing efforts specifically on the critical path timing relationships by using a dedicated testing clock signal. Instead of applying comprehensive ATPG patterns to the entire system, the testing methodology concentrates resources on verifying timing-critical paths, thereby maintaining high testing coverage for essential functions while significantly reducing overall testing time and cost
Data Source
AI summary
A memory-testing device for testing a memory is provided. The memory-testing device includes a testing circuitry and a register. The testing circuitry is coupled to the memory for testing performance of the memory. The register is coupled to the testing circuitry and inputted by a testing clock signal, wherein the testing clock signal is different from an original clock signal of the memory and/or the testing circuitry. The testing clock signal is utilized for adjusting the time when the memory-testing device latches data from the memory to decrease a timing slack of the memory-testing device.