Memory Testing Data Compression Circuit with Cross-Bank Comparison
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Solution Overview
Problem
Current memory testing methods using data compression are limited by inflexible test patterns and reduced visibility into actual data read from memory cells, as they require comparison of identical data values, failing to detect errors when multiple memory cells fail simultaneously.
Innovation Solution
A data compression circuit with latch test circuits and a comparator that allows configurable testing using various test patterns, enabling flexible memory testing by applying a test mask and prefetching memory data to latch and compare data from multiple global data lines, and generating error flags for defective memory detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data compression is used during memory testing by comparing data written to memory bit cells against one another, then testing efficiency is improved, but flexibility in test patterns is limited and visibility into verification of actual data read from memory cells is reduced
Solution Approach 1:
The patent divides the memory array into multiple banks (first bank and second bank) that can be independently tested. Each bank can undergo compression testing simultaneously, allowing the system to maintain high testing efficiency while applying different test patterns to different banks, thus improving flexibility without sacrificing productivity.
Solution Approach 2:
The patent implements a universal testing architecture that supports both traditional compression testing (comparing data within a bank) and cross-bank testing (comparing data between banks). This multi-functional approach allows the same hardware to execute various test patterns including address reversal, bit reversal, and complement patterns, resolving the contradiction between efficiency and flexibility.
2Speed
If data compression testing compares data written to memory bit cells against one another, then testing speed is improved, but detection capability for simultaneous failures in multiple memory cells is reduced
Solution Approach 1:
The patent introduces an intermediary comparison mechanism where data from first memory cells in a first bank is compared against data from second memory cells in a second bank. This intermediary cross-bank comparison approach maintains fast testing speed while improving error detection capability, as it can identify patterns of failure that would be missed by traditional within-bank compression testing alone.
Solution Approach 2:
The patent performs both traditional compression testing (partial action) and additional cross-bank comparison testing (excessive action). By implementing more comprehensive testing than the minimum required, the system maintains high speed through parallel execution while enhancing error detection capability through the additional comparison layer.
3Loss of information
If traditional memory testing methods are used without data compression, then visibility into actual data read from memory cells is maintained, but testing efficiency and productivity are reduced
Solution Approach 1:
The patent adds a new dimension to traditional memory testing by implementing cross-bank comparison in addition to traditional within-bank compression testing. This dimensional expansion allows the system to maintain full visibility into actual data read from memory cells while significantly improving testing efficiency through parallel processing of multiple banks with different test patterns.
Data Source
AI summary
Apparatuses and methods for memory testing with data compression is described. An example apparatus includes a plurality of latch test circuits, wherein each of the plurality of latch test circuits is coupled to a corresponding global data line of a memory. Each of the latch test circuits is configured to receive test data and is configured to latch data from the corresponding global data line or a corresponding mask bit. Each of the plurality of latch test circuits is further configured to output data based at least in part on the corresponding mask bit. A comparison circuit is coupled to an output of each of the latch test circuits and is configured to compare output data provided by each of the latch test circuits and provide a comparator output having a logical value indicative of whether all the output data matches.