Memory Testing System with Dual Circuit Units for Rewritable Non-Volatile Memory
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Solution Overview
Problem
The existing testing processes for rewritable non-volatile memory modules are separate and independent for higher-level and lower-level storage devices, making it inefficient to determine which type of storage device a module is applicable to.
Innovation Solution
A memory testing method and system that integrates two memory controlling circuit units to test a rewritable non-volatile memory module, allowing for the sharing of test information to quickly and accurately determine its applicability to different types of storage devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate and independent testing processes are used for higher-level and lower-level storage devices, then each testing process can be optimized for its specific requirements, but the overall testing time and flow increase
Solution Approach 1:
The patent combines separate testing processes for higher-level and lower-level storage devices into a single integrated testing system. The memory controlling circuit unit can perform both types of testing sequentially using the same hardware infrastructure, eliminating the need for separate testing lines and reducing overall testing time while maintaining the optimized testing criteria for each storage device type.
Solution Approach 2:
The memory controlling circuit unit is designed with multi-functionality to handle both higher-level and lower-level storage device testing. By incorporating universal testing capabilities that can adapt to different storage device types, the system achieves time savings while preserving the specialized testing accuracy required for each application level.
2Reliability
If separate and independent testing processes are used for higher-level and lower-level storage devices, then each testing process can be independently optimized, but the testing flow becomes more complex
Solution Approach 1:
The patent merges multiple independent testing processes into a unified testing flow managed by a single memory controlling circuit unit. This integration simplifies the overall testing architecture by eliminating redundant components and streamlining the sequential operations, reducing flow complexity while maintaining the ability to perform specialized testing for different storage device levels.
3Productivity
If multiple memory controlling circuit units are integrated to test different storage device types, then testing efficiency improves, but the device complexity increases
Solution Approach 1:
The patent implements a universal memory controlling circuit unit that can perform multiple testing functions for different storage device types. This multi-functional approach increases testing efficiency by consolidating operations into a single unit while avoiding the complexity that would arise from integrating multiple separate circuit units, as the universal design shares common resources and control logic.
Data Source
AI summary
A memory testing method and a memory testing system. The memory testing system includes a host system and a testing device. The host system includes a processor. The testing device is coupled to the host system and a rewritable non-volatile memory module. A first memory controlling circuit unit corresponding to a first type memory storage device in the testing device tests the rewritable non-volatile memory module to obtain first test information. A second memory controlling circuit unit corresponding to a second type memory storage device in the testing device tests the rewritable non-volatile memory module to obtain second test information according to the first test information. The processor determines that whether the rewritable non-volatile memory module is applicable to the second type memory storage device or not according to the first test information and the second test information.