Memory Testing Method for ECC Storage Devices
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Solution Overview
Problem
Memory storage devices with error correction code (ECC) functions face reduced test coverage and extended testing time due to the inability to control data bits and verification bits to have a predetermined form simultaneously during memory cell testing.
Innovation Solution
A memory testing method that writes first data into multiple segments and second data into a separate segment, allowing for controllable data content, and uses a data converting circuit to convert read data into check data encoded by an ECC circuit, enabling efficient inspection of memory cells while maintaining ECC functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple sets of test data in specific forms are written into memory cells to test for abnormal leakage current, then testing thoroughness is improved, but for memory storage devices with ECC function, data bits and verification bits cannot be controlled to have predetermined forms simultaneously, resulting in reduced test coverage and extended testing time
Solution Approach 1:
The patent segments the memory array into multiple first segments and a second segment, allowing independent control of data written to each segment. This enables the first segments to contain controllable test data while the second segment contains corresponding check data, resolving the contradiction between maintaining test coverage and reducing testing time for ECC-equipped memory devices
Solution Approach 2:
The patent introduces a data converting circuit as an intermediary between the memory array and the decoding circuit. This circuit converts read data from the second segment into check data that corresponds to the encoded first data, enabling efficient verification without requiring simultaneous control of all data bits and verification bits in predetermined forms
2Reliability
If data bits and verification bits are controlled to have predetermined forms simultaneously in ECC memory devices, then test coverage is improved, but the inability to do so results in extended testing time
Solution Approach 1:
By dividing the memory array into first segments for data and a second segment for check data, the patent enables independent control and testing of each segment. This segmentation allows the use of controllable test data patterns in the first segments while generating corresponding check data in the second segment, thereby maintaining high test coverage without extending testing time
Solution Approach 2:
The patent performs preliminary encoding of test data using the encoding circuit to generate corresponding check data before writing to the memory array. This preliminary action ensures that when data and verification bits are read back, they can be efficiently verified against the pre-computed check data, improving both reliability and productivity
Data Source
AI summary
A memory storage device and a memory testing method for testing a memory array of the memory storage device are provided. The memory testing method includes the following steps: writing first data into a plurality of first segments of the memory array, and writing second data to a second segment of the memory array; obtaining third data by reading the plurality of first segments, and obtaining fourth data by reading the second segment; converting the fourth data to fifth data, wherein the fifth data is the same as check data obtained by encoding the first data by using an encoding circuit corresponding to a decoding circuit of the memory storage device.