Memory Testing Circuit Encoding Main and Parity Bits
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Solution Overview
Problem
Memory testing using error correcting codes (ECC) schemes requires separate reading of main bits and parity bits, doubling the read time and reducing testing efficiency.
Innovation Solution
A memory testing method and apparatus that encodes test data into encoded data including a first piece indicating the binary state and a second piece indicating error bits, allowing for efficient extraction of necessary information without the need for a second read operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If main bits and parity bits are read separately for testing in ECC memory, then testing completeness is improved, but testing time increases
Solution Approach 1:
The patent combines the reading of main bits and parity bits into a single read operation by encoding them together into encoded data. The auxiliary testing circuit encodes the test data including both main bits and parity bits simultaneously, allowing both to be tested in one read cycle rather than requiring separate read operations, thus reducing testing time while maintaining testing completeness
Solution Approach 2:
The patent performs preliminary encoding of test data into encoded data that contains both main bits and parity bits before the read operation. This preliminary encoding action prepares the data in advance so that when the read occurs, both main bits and parity bits are already packaged together, eliminating the need for a second read operation and reducing overall testing time
Data Source
AI summary
A memory testing method for testing a memory apparatus configured with an auxiliary testing circuit is provided. The memory testing method includes: reading a test data from a memory array of the memory; and encoding the test data into an encoded data by the auxiliary testing circuit, wherein the encoded data comprises a first piece data and a second piece data. The encoded data is encoded to include a first piece data and a second piece data, where the first piece data indicates a number of a binary state in the read test data, and the second piece data indicates an error bit in the read test data. In addition, a memory apparatus for the memory testing method is also provided.