Semiconductor Memory Testing Error Log Compression
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Solution Overview
Problem
Current semiconductor testing systems are limited in their ability to concurrently test both volatile and non-volatile memory devices, and they fail to replicate the conditions under which memory failures occur in end-user products, making it difficult to predict and address end-user needs.
Innovation Solution
A dynamic real-time testing system that includes a Master Controller Unit (MCU) managing one or more Slave Controller Units (SCU) capable of testing both volatile and non-volatile memories. The system can reconfigure its I/O pins and operational frequencies dynamically, performing different real-time testing patterns for various memory types and running end-user applications to mimic the target host environment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional semiconductor testing systems are used, then testing can be performed on memory devices, but the systems cannot concurrently test both volatile and non-volatile memory devices and cannot replicate end-user product conditions
Solution Approach 1:
The testing system is designed to universally test both volatile and non-volatile memory devices using a single integrated platform. The system incorporates multiple testing modes that can be dynamically selected, allowing the same hardware infrastructure to perform different types of memory testing (DC level testing, AC timing testing, functional testing) without requiring separate dedicated testing systems for each memory type.
Solution Approach 2:
The testing system is divided into distinct functional modules including DC level testing capabilities, AC timing testing capabilities, and functional testing capabilities. Each module can operate independently or in combination, allowing the system to address different testing requirements through modular architecture rather than requiring a completely integrated monolithic system.
2Reliability
If generic testers with fixed functional test patterns are used, then standard industry testing can be performed, but the testers cannot replicate real-world end-user conditions or predict end-user failures
Solution Approach 1:
The testing system transitions from static fixed test patterns to dynamic adaptive testing. The system can dynamically load and execute different test patterns including actual end-user applications, allowing testing conditions to adapt to real-world usage scenarios. This dynamic capability enables the system to replicate varying workloads, temperature conditions, and operational modes that occur in actual product deployment.
Solution Approach 2:
The system enables changes in testing parameters such as temperature, voltage, and operational modes to match real-world conditions. By varying these parameters during testing, the system can simulate different end-user environments and identify failures that only occur under specific operational conditions rather than under fixed standard test parameters.
3Measurement precision
If comprehensive error logging is performed during memory testing, then all errors can be detected and recorded, but the required storage space becomes excessively large
Solution Approach 1:
The system extracts and isolates only the essential error information from comprehensive test data. Rather than logging all raw test data and error details, the system identifies and extracts key error patterns, failure modes, and critical information that indicate manufacturing defects or reliability issues. This selective extraction reduces storage requirements while maintaining the ability to diagnose problems effectively.
Solution Approach 2:
The system implements partial logging by focusing on recording only the most significant error types and failure patterns rather than attempting to log every possible error detail. This approach captures sufficient information to identify and categorize manufacturing defects while avoiding the storage overhead of comprehensive exhaustive logging of all test data points.
Data Source
AI summary
A memory testing device uses a master control unit (MCU) to concurrently operate multiple, intelligent, slave control units (SCUs). The MCU or an SCU translates memory addresses of a device under test (DUT) into a matrix. The SCU accumulates error data by testing a test bit of the memory across multiple cells of the matrix, the accumulated error data is post-processed to determine if the test bit is faulty, and the process is repeated for additional test bits. The post-processed data is analyzed to identify one or more of the test bits as faulty, and then include in a test log preferably only a single instance of a memory address that corresponds to each of the one or more faulty test bits.