Memory Testing Method for I/O Fail Identification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory-testing methods cannot identify input/output (I/O) fails in emerging memory circuits, which affects the reliability of memory due to continuous read errors originating from peripheral circuits, even when ECC can recover data.
Innovation Solution
A memory-testing method that selects sampled row and column addresses using selection logic, executes read operations on both blocks, and determines read fail rates to mark blocks as input/output fails if exceeding a predetermined ratio, distinguishing between solid and soft failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If current memory-testing methods are used, then the testing process is simple, but I/O fails cannot be identified
Solution Approach 1:
The patent segments the memory array into multiple blocks (first block, second block, etc.) and performs separate read operations on each block. This segmentation allows the testing method to identify which specific block has an I/O fail by comparing read fail rates across different blocks, thereby improving measurement precision while maintaining manageable complexity through systematic division of the testing process.
Solution Approach 2:
The patent performs read operations on sampled row addresses and sampled column addresses, which represents a partial action approach. Instead of testing every single address in the memory array, it selects representative samples to determine read fail rates. This partial action approach enables I/O fail identification without requiring exhaustive testing of all memory locations, thus improving detection capability while controlling testing complexity.
2Reliability
If ECC technology is used to recover data, then data can be recovered from I/O fails, but the reliability of the memory circuit is still influenced
Solution Approach 1:
The patent implements a feedback mechanism by determining read fail rates from read operations and using this information to identify blocks with I/O fails. The testing method provides feedback about the location and nature of I/O failures, allowing the system to distinguish between solid I/O fails and soft I/O fails. This feedback enables better reliability management by providing actionable information about peripheral circuit issues, complementing ECC's data recovery capability.
3Measurement precision
If read operations are executed on all memory blocks, then comprehensive testing is achieved, but testing time increases
Solution Approach 1:
The patent executes read operations on sampled row addresses and sampled column addresses rather than all possible addresses. This partial action approach tests representative samples from each block to determine read fail rates, enabling I/O fail detection without requiring exhaustive testing of every memory location. The sampling strategy achieves comprehensive I/O fail identification while significantly reducing the number of read operations required.
Solution Approach 2:
The patent segments the testing process by dividing it into separate read operations on different blocks with different address patterns (row addresses for one block, column addresses for another block). This segmentation allows parallel or sequential execution of tests on multiple blocks, improving detection accuracy through comprehensive block coverage while managing testing time through structured organization of test operations.
Data Source
AI summary
A memory-testing method is adapted in a memory circuit including a first block and a second block including a plurality of row addresses and column addresses. The memory-testing method includes: selecting one of the row addresses and one of the column addresses as a testing row and a testing column according to selection logic; selecting sampled column addresses of the testing row and sampled row addresses of the testing column according to a sampling process; executing the read operation on the sampled column addresses of the testing row and the sampled row addresses of the testing column in the first block; determining whether the read fail rate of the first block exceeds a predetermined ratio; and marking the first block as an input/output fail when the read fail rate exceeds the predetermined ratio.