Memory Testing Logic Interrupt Latency Reduction
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Solution Overview
Problem
Existing memory testing mechanisms in data processing systems suffer from significant interrupt latency due to the need for memory tests to complete before the processing logic can respond to system events, which is critical in real-time systems where quick reaction is essential.
Innovation Solution
Incorporating memory testing logic that can detect system events during transparent testing routines, allowing the test to be stopped and the memory restored to its initial state, enabling the processing logic to access the memory sooner and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory testing logic performs a complete transparent testing routine before allowing processing logic to access memory, then memory defects are reliably detected, but interrupt latency increases significantly
Solution Approach 1:
The memory testing logic performs preliminary actions by detecting system events during the testing routine and restoring memory to its initial state before processing logic needs to access it. This preliminary restoration action allows the system to respond to interrupts without completing the full testing sequence, thereby reducing interrupt latency while maintaining memory reliability through the restoration capability.
2Reliability
If transparent BIST algorithms access each address multiple times (15N or 22N) to ensure thorough testing, then memory reliability is improved, but interrupt latency increases proportionally
Solution Approach 1:
The testing logic dynamically adapts the testing process by monitoring for system events during execution. When a system event is detected, the testing routine is interrupted and memory is restored to its initial state, making the effective test duration dynamic rather than fixed. This dynamic approach allows the system to balance testing thoroughness with responsive interrupt handling based on real-time system conditions.
3Measurement precision
If processing logic is prohibited from accessing memory during the entire testing routine, then testing accuracy is maintained, but system productivity decreases
Solution Approach 1:
The memory testing logic performs preliminary restoration of memory to its initial state when system events are detected, before processing logic needs to access the memory. This preliminary action allows the system to maintain testing accuracy through proper memory state management while improving productivity by enabling timely processor access rather than waiting for complete testing.
Data Source
AI summary
This application discloses a data processing apparatus comprising: at least one memory; processing logic operable to perform data processing operations on data and operable to access said at least one memory; and memory testing logic operable to perform a transparent algorithm testing routine on said at least one memory, said data processing apparatus impeding said processing logic from accessing said at least one memory while said memory testing logic is performing said testing routine; wherein said processing logic and said memory testing logic are operable to detect a system event, said memory testing logic being operable when performing said testing routine to respond to detection of said system event by stopping said testing routine and restoring said at least one memory to an initial state, said initial state being a state it was in immediately prior to commencement of said testing routine, whereupon said data processing apparatus is operable to allow said processing logic to access said at least one memory.