Memory Testing Circuit Single Pin Parallel Signal Encoding
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Solution Overview
Problem
Conventional memory testing methods require multiple signal pins, leading to increased testing time and cost as the density of chip dies on a single wafer increases, necessitating a reduction in testing time and cost while maintaining high test efficiency.
Innovation Solution
A memory testing circuit and method utilizing a single signal pin, incorporating a VPPIO I/O module and self-test circuit to encode and decode signals, enabling parallel testing of multiple memory devices by converting a serial input into a parallel signal and providing a clock signal for effective memory testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple signal pins are used for memory testing, then testing capability and parallelism are improved, but testing cost and time per wafer increase due to higher pin requirements
Solution Approach 1:
The patent combines multiple testing functions (serial input, parallel output, clock generation, encoding/decoding) into a single integrated testing circuit module that can be implemented within the memory device itself. This merging of functions allows the memory device to perform self-testing, eliminating the need for multiple external signal pins and reducing testing time per wafer while maintaining high testing capability.
Solution Approach 2:
The testing circuit is designed with multi-functionality, where a single signal pin can serve multiple purposes through encoding and decoding operations. The circuit can handle both serial and parallel signal modes, generate clock signals internally, and perform various testing operations, thereby improving productivity without requiring additional pins that would increase testing cost and time.
2Productivity
If multiple signal pins are used for memory testing, then testing capability is improved, but testing cost increases
Solution Approach 1:
The patent merges multiple testing functions into a single integrated circuit module that can be fabricated within the memory device. This consolidation reduces the number of external signal pins required, thereby lowering testing equipment complexity and manufacturing costs while maintaining comprehensive testing capability.
Solution Approach 2:
The memory device incorporates a self-testing capability through the integrated testing circuit that can perform self-diagnosis and self-testing operations. This self-service approach eliminates the need for complex external testing equipment with multiple signal pins, reducing both manufacturing cost and testing capability requirements.
3Loss of time
If a single signal pin is used for memory testing, then testing cost and time are reduced, but signal encoding and decoding complexity increases
Solution Approach 1:
The patent combines encoding, decoding, clock generation, and testing control functions into a single integrated testing circuit module. This merging reduces the overall system complexity despite the increased sophistication of individual components, as the entire testing functionality is consolidated within the memory device rather than requiring complex external equipment.
Solution Approach 2:
The testing circuit acts as an intermediary between the single signal pin and the memory array, performing encoding/decoding operations internally. This intermediary approach simplifies the external interface while managing the complexity of signal transformation within the device, reducing both testing time and overall system complexity.
Data Source
AI summary
A memory testing circuit and method are disclosed, the redesigning of a memory to be tested through incorporation therein a testing circuit includes a self-test circuit incorporating a decoder circuit, and a VPPIO I/O module incorporating an encoder circuit and having multiple functions including digital I/O, high analog voltage I/O and current I/O. An oscillator module embedded in the multiplexer circuit provides a clock signal for the testing. The VPPIO I/O module is configured to convert, by the self-test circuit, a stimulating input from a single signal pin to a parallel signal recognizable by the memory and an analog voltage/current signal, thereby accomplishing proper testing of the memory. This enables a single signal pin to test all functions of one memory, thereby increasing the number of memory dies on a wafer tested in parallel by a test instrument and reducing the testing time per wafer as well as testing cost.