Nonvolatile Memory Thread Allocation for Write Amplification
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Solution Overview
Problem
Current semiconductor storage devices face challenges in reducing the number of data writes and erases, which affects reliability and performance, and there is a need to minimize the circuit size of the memory controller to optimize cost and power consumption.
Innovation Solution
The semiconductor storage device employs a nonvolatile memory with multiple threads, each having a buffer region for write data, and a controller that allocates stream data based on priority levels, writing data from these buffers to memory regions efficiently to minimize write amplification and optimize thread allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is written frequently to nonvolatile semiconductor memory, then data can be stored and accessed, but the reliability decreases and read/write performance deteriorates due to wear
Solution Approach 1:
The memory device is divided into multiple memory regions (first memory region and second memory region) with different endurance characteristics. Frequently written data is stored in the first memory region with higher endurance, while less frequently written data is stored in the second memory region. This segmentation allows the system to maintain high reliability for critical data while still providing data storage functionality, thereby resolving the contradiction between productivity and reliability.
2Adaptability or versatility
If the circuit size of memory controller is increased, then more sophisticated data management is possible, but cost and power consumption increase
Solution Approach 1:
The memory device autonomously manages data allocation between different memory regions based on write frequency characteristics. The control unit automatically determines which data should be stored in which memory region without requiring complex external control circuits. This self-service approach enables sophisticated data management while keeping the memory controller circuit size minimal, resolving the contradiction between adaptability and device complexity.
3Device complexity
If multiple threads share the same buffer region, then circuit size is reduced, but write amplification factor increases
Solution Approach 1:
The buffer memory is segmented into multiple buffer regions corresponding to different threads. Each thread has its own dedicated buffer region, preventing buffer conflicts and reducing write amplification. This segmentation of the buffer memory allows the system to maintain low write amplification factor while keeping the overall circuit size manageable through efficient memory sharing architecture.
Data Source
AI summary
A semiconductor storage device comprises a nonvolatile semiconductor memory with memory regions, threads, and a controller. Each thread includes a buffer region in which write data from a host are stored before the write data are written to one of the memory regions, and the buffer region of each thread is different from buffer regions of the other threads. The controller receives stream data from the host, each stream data being associated with one of multiple stream identifications, allocates each stream identification to one of the threads according to priority levels assigned to the stream identifications, such that a stream identification assigned a highest priority level is allocated to a thread to which none of other stream identifications are allocated, and writes each stream data stored in the buffer regions to one of the memory regions according to stream identification of the stream data.