Memory Read Threshold Calibration Using Parallel Decoder Pools
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Solution Overview
Problem
The increasing complexity of read threshold calibration in memory devices due to higher QoS requirements and wordline-to-wordline variation leads to increased latency and bit error rates, burdening the system with frequent calibration operations.
Innovation Solution
Implementing a memory controller with a decoder pool that generates and divides bit-error-rate estimation scan hypotheses among multiple decoders to adjust read locations based on received BER results, thereby reducing latency and improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional single-decoder read threshold calibration is used, then device complexity is low, but latency increases and calibration accuracy decreases
Solution Approach 1:
The patent divides the calibration workload into multiple segments by using a pool of decoders (e.g., 4 decoders) that process different portions of the calibration data simultaneously. Each decoder handles a subset of the BES hypotheses for a given wordline, enabling parallel processing and reducing overall calibration latency.
Solution Approach 2:
The patent combines multiple decoders into a unified decoder pool that shares common control logic and data structures. The controller circuit coordinates multiple decoders to work together on the same calibration task, merging their computational resources to achieve faster calibration while maintaining manageable system complexity through centralized control.
2Reliability
If read threshold calibration is performed frequently to maintain accuracy, then reliability improves, but productivity decreases due to time consumption
Solution Approach 1:
By segmenting the calibration workload across multiple decoders, the system can complete calibration operations faster, allowing frequent calibration without sacrificing throughput. The parallel processing capability enables the system to maintain high read accuracy while minimizing the time spent on calibration operations.
Solution Approach 2:
The decoder pool enables continuous calibration operations to proceed with minimal interruption to normal read operations. Multiple decoders can service different wordlines simultaneously, ensuring that calibration is an ongoing process that maintains reliability without creating bottlenecks in the overall system throughput.
3Measurement precision
If more BES hypotheses are tested to improve calibration accuracy, then measurement precision improves, but loss of time increases
Solution Approach 1:
The patent segments the evaluation of BES hypotheses across multiple decoders, allowing the system to test a larger number of hypotheses in parallel. Each decoder evaluates a subset of hypotheses simultaneously, enabling comprehensive accuracy assessment without linearly increasing the time required.
Solution Approach 2:
The patent adds the dimension of parallel processing by deploying multiple decoders across different processing units. This transforms the calibration process from a sequential single-decoder approach to a parallel multi-decoder architecture, enabling the system to evaluate more hypotheses without proportionally increasing calibration time.
Data Source
AI summary
A memory controller includes, in one embodiment, a memory interface, a plurality of decoders, and a controller circuit. The memory interface is configured to interface with a memory having a plurality of wordlines. Each decoder of the plurality of decoders is configured to determine a bit error rate (BER). The controller circuit configured to generate a plurality of bit-error-rate estimation scan (BES) hypotheses for one wordline of the plurality of wordlines, divide the plurality of BES hypotheses among the plurality of decoders, receive BER results from the plurality of decoders based on the plurality of BES hypotheses, and adjust one or more read locations of the one wordline based on the BER results from the plurality of decoders.