Memory Cell Threshold Calibration for Charge Leakage Repair
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Solution Overview
Problem
Conventional volatile memory devices face issues with charge leakage due to variations in transistor structure and material, leading to failed memory cells that cannot properly store or retain information, resulting in reduced yield and increased error rates.
Innovation Solution
The memory device incorporates on-die circuitry to detect and repair failed memory cells by adjusting the threshold voltage of transistors, using a calibration operation that includes a detection stage, a repair stage, and a verification stage, and employs error-correction code engines to improve yield and reduce bit error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If failed memory cells are discarded to maintain quality, then error rates are reduced, but manufacturing yield decreases
Solution Approach 1:
The invention converts the harmful effect of manufacturing variations that cause excessive charge leakage into a beneficial outcome by using calibration operations to detect and repair affected memory cells. The stress conditions applied during repair adjust transistor threshold voltages to bring leakage within acceptable ranges, turning previously failed cells into functional ones and improving yield without compromising error rates
2Reliability
If transistor structure and material variations are reduced to minimize charge leakage, then memory cell reliability is improved, but manufacturing complexity and cost increase
Solution Approach 1:
Instead of controlling physical transistor parameters during manufacturing, the invention changes operational parameters by applying stress conditions during calibration operations. The repair stage uses voltage stress and temperature stress to dynamically adjust transistor threshold voltages, compensating for manufacturing variations without requiring tighter process control or more complex manufacturing steps
Data Source
AI summary
Some embodiments include apparatuses and methods using the apparatuses. One of the embodiments includes a capacitor, a transistor coupled to the capacitor, the transistor and the capacitor included in a memory cell; the transistor including a channel structure, a gate including a portion located on a side of the channel structure, and a dielectric structure between the channel structure and the gate; and on-die circuitry configured to selectively apply a stress condition to the transistor to tune a threshold voltage of the transistor.