Memory Read Threshold Offsets for Wordline Group Error Avoidance
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Solution Overview
Problem
Memory devices experience increasing bit error rates due to slow charge loss and non-uniform threshold voltage distribution shifts across wordline groups, making it difficult to predict an optimal threshold voltage offset for error correction without compromising performance.
Innovation Solution
Assign each wordline group of a block to a corresponding block family, applying a threshold voltage offset specific to the group to account for variations in threshold voltage distribution shifts, and update these offsets during read operations to improve error handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single threshold voltage offset is used for error correction, then the error correction mechanism is simple, but it cannot account for non-uniform threshold voltage distribution shifts across different wordline groups, leading to increased read errors
Solution Approach 1:
The patent divides the memory device into multiple wordline groups, each assigned to a specific block family. Each wordline group receives a dedicated threshold voltage offset tailored to its specific charge loss characteristics. This segmentation allows the system to address non-uniform threshold voltage distribution shifts across different regions of the memory device, thereby reducing read errors while maintaining manageable complexity through structured organization.
Solution Approach 2:
The patent implements local quality by assigning unique threshold voltage offsets to different block families based on their specific charge loss patterns. Instead of using a uniform offset for the entire memory device, each wordline group receives customized offset values that account for local variations in threshold voltage distribution. This approach optimizes error correction performance for each specific region while acknowledging the increased complexity in managing multiple localized parameters.
2Reliability
If threshold voltage offsets are updated during read operations, then error handling performance improves, but the time required for read operations increases
Solution Approach 1:
The patent applies preliminary action by pre-calculating and pre-storing optimal threshold voltage offsets for each block family before actual read operations occur. These offsets are determined based on charge loss characteristics and temperature conditions, allowing the system to retrieve and apply the correct offset immediately during read operations without performing time-consuming calculations in real-time. This significantly reduces read operation time while maintaining high error handling performance.
Solution Approach 2:
The patent implements feedback mechanisms where the system monitors read error rates and adjusts threshold voltage offsets accordingly. When read errors are detected, the system uses this feedback information to refine and update the offset values for subsequent operations. This continuous feedback loop improves error handling performance over time while the system works to minimize the time impact by using cached offset values and incremental updates rather than complete re-calculations.
3Adaptability or versatility
If adaptive block family error avoidance is implemented, then reliability in varying charge loss and temperature conditions improves, but device complexity increases
Solution Approach 1:
The patent implements dynamics by creating a flexible error avoidance mechanism that adapts to varying charge loss conditions and temperature changes. The system dynamically selects appropriate threshold voltage offsets based on real-time detection of charge loss patterns and temperature information. This dynamic adaptation allows the memory device to maintain optimal performance across different operating conditions while managing complexity through structured decision-making frameworks and pre-established offset mappings for various condition scenarios.
Data Source
AI summary
A system includes a memory device and a processing device operatively coupled with the memory device to perform operations including receiving a read command specifying a logical address; translating the logical address into a physical address referencing a physical block stored on the memory device; identifying a wordline group associated with the physical address; identifying, based on block family metadata associated with the memory device, a block family associated with the physical block and the wordline group; determining a first threshold voltage offset associated with the block family; and reading, using the first threshold voltage offset, data from the physical block.