Semiconductor Memory Threshold Voltage Pairing for 3-Bit Storage

Solution Overview

Problem

Existing NAND-type flash memories face challenges in efficiently storing multiple bits of data per memory cell due to limitations in threshold voltage distributions, leading to inefficiencies in data storage and retrieval operations.

Innovation Solution

The semiconductor memory system employs a configuration with two memory cell arrays, where each memory cell has threshold voltages set to one of three levels, allowing for the storage and retrieval of 3-bit data using combinations of threshold voltages in paired memory cells across two planes, enhancing data storage capacity and efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If traditional NAND-type flash memory with limited threshold voltage levels is used, then device complexity is reduced, but data storage capacity per memory cell is limited

Engineering Contradiction:

Improvedata storage capacityVSAvoidthreshold voltage distribution complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent introduces a new dimension by implementing two distinct threshold voltage distributions (first and second distributions) within the same memory cell array. This allows memory cells to operate in multiple threshold voltage states (first, second, and third threshold voltages), enabling 3-bit storage per cell through combinatorial encoding across two memory cell arrays, thereby increasing storage capacity without proportionally increasing physical device complexity

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent changes the threshold voltage parameter by establishing two separate threshold voltage distributions with different voltage ranges. The first distribution has a first threshold voltage range, while the second distribution has a second threshold voltage range that is higher than the first. This parameter differentiation enables distinct threshold voltage states (Vth1, Vth2, Vth3) that can be combined to store 3-bit data, resolving the contradiction between storage capacity and device complexity

Inventive Principle:

Principle #35Parameter changes

2Quantity of substance

If threshold voltage levels are increased to store more bits per cell, then data storage capacity improves, but measurement precision requirements increase

Engineering Contradiction:

Improvedata storage capacityVSAvoidthreshold voltage discrimination precision

Core Design Contradiction:

Quantity of substanceVSMeasurement precision

Solution Approach 1:

The patent segments the threshold voltage spectrum into two distinct distributions: a first threshold voltage distribution with a first threshold voltage range, and a second threshold voltage distribution with a second threshold voltage range higher than the first. This segmentation creates well-separated voltage bands that reduce overlap between states, thereby maintaining measurement precision while enabling 3-bit storage capacity through combinatorial encoding

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by assigning different threshold voltage characteristics to different memory cell arrays (first array with first distribution, second array with second distribution). Each array is optimized for its specific threshold voltage range, allowing precise discrimination within each local distribution while achieving high overall storage capacity through the combination of both arrays

Inventive Principle:

Principle #3Local quality

3Productivity

If multiple threshold voltage distributions are implemented, then data storage efficiency improves, but manufacturing precision requirements increase

Engineering Contradiction:

Improvedata storage efficiencyVSAvoidthreshold voltage control precision

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The patent introduces a new dimension by implementing two distinct threshold voltage distributions (first and second distributions) within the same memory cell array. This allows memory cells to operate in multiple threshold voltage states (first, second, and third threshold voltages), enabling 3-bit storage per cell through combinatorial encoding across two memory cell arrays, thereby increasing storage capacity without proportionally increasing physical device complexity

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent changes the threshold voltage parameter by establishing two separate threshold voltage distributions with different voltage ranges. The first distribution has a first threshold voltage range, while the second distribution has a second threshold voltage range that is higher than the first. This parameter differentiation enables distinct threshold voltage states (Vth1, Vth2, Vth3) that can be combined to store 3-bit data, resolving the contradiction between storage capacity and device complexity

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS20250384937A1Semiconductor memory with different threshold voltages of memory cells

Publication Date: 2025.12.18 KIOXIA CORP

AI summary

According to one embodiment, a semiconductor memory includes a first memory cell array including a plurality of first memory cells; and a second memory cell array including a plurality of second memory cells. Each of threshold voltages of the first memory cells and the second memory cells is set to any of a first threshold voltage, a second threshold voltage higher than the first threshold voltage, and a third threshold voltage higher than the second threshold voltage. Data of three or more bits including a first bit, a second bit, and a third bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.