Semiconductor Memory Device Threshold Voltage Control
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently controlling threshold voltages of memory cells during erase, write, and verify operations, leading to misreads and deviations in threshold distributions between memory cells, which affect data storage and retrieval accuracy.
Innovation Solution
The semiconductor memory device employs a specific voltage control method involving erase, write, and verify operations, including both-side EP and single-side EP write operations, to adjust threshold voltages by applying distinct program voltages to word lines WLI and WLO, ensuring accurate data storage and retrieval by aligning threshold distributions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional voltage control methods are used during erase and write operations, then memory operations can be performed, but threshold voltage deviations and misreads occur due to inefficient control
Solution Approach 1:
The patent applies different program voltages to different word lines during write operations. Specifically, a first program voltage is applied to a first word line while a second program voltage (different from the first) is applied to a second word line. This parameter change approach allows precise control of threshold voltages in different memory cell regions, preventing threshold distribution deviations and improving both reliability and manufacturing precision.
2Reliability
If standard erase and write operations are performed without differentiated voltage control, then memory operations are simpler, but misreads occur due to unaligned threshold distributions
Solution Approach 1:
The patent segments the voltage control process by applying different program voltages to different word lines. The memory device divides the write operation into multiple voltage control stages, where each word line receives a specifically tailored voltage. This segmentation enables precise threshold voltage control in different regions, aligning threshold distributions and eliminating misreads, while the complexity is managed through systematic voltage control.
3Ease of operation
If uniform program voltages are applied to all word lines, then voltage control is easier, but threshold voltage deviations occur between memory cells
Solution Approach 1:
The patent implements local quality by applying different program voltages to different word lines based on their specific requirements. Instead of uniform voltage application, each word line receives a locally optimized voltage level. This approach maintains threshold voltage uniformity across memory cells by accounting for local variations, while the ease of operation is preserved through automated voltage control mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures precise control over threshold voltages, reducing misreads and maintaining accurate data storage by aligning the threshold distributions of memory cells MCI and MCO, thereby enhancing the reliability and efficiency of memory operations.
Implementation Method 1
a gate insulating layer provided between the conductive layers and the semiconductor layer. The gate insulating layer comprises a memory portion configured to store data
Data Source
AI summary
A semiconductor memory device comprises: a semiconductor layer extending in a first direction; a first and second conductive layer facing the semiconductor layer from one side and the other side in a second direction; and a charge storage layer comprising portions provided between the semiconductor layer and first conductive layer and between the semiconductor layer and second conductive layer. The semiconductor memory device is configured to execute erase operation, first write operation, and second write operation. In the first write operation, the first and second conductive layers are applied with first program voltage. In the second write operation, the first conductive layer is applied with second program voltage, and second conductive layer is applied with second voltage lower than the second program voltage. The second write operation is executed after execution of the erase operation and before execution of the first write operation.