Semiconductor Memory Device Threshold Voltage Range Encoding
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Solution Overview
Problem
Existing nonvolatile memory devices face inefficiencies in data output during read operations, particularly when correcting fail bits, due to the need for multiple data output processes across various regions, leading to increased timing issues and reduced utilization of memory cell regions.
Innovation Solution
A method and device that divide threshold voltage distributions of memory cells into multiple ranges using a series of read voltages, allowing for data encoding without additional circuitry, enabling infinite range recognition and reduced data output times by sequentially storing and outputting data '0' and '1' in latch groups based on threshold voltages, thereby facilitating efficient error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple data output processes are performed for each region to correct fail bits, then error correction capability is improved, but timing issues increase and operational efficiency deteriorates
Solution Approach 1:
The patent segments the threshold voltage distribution into multiple ranges (first to eighth ranges) and uses separate latch groups to detect and encode data for each range simultaneously. This allows parallel processing of different error regions, maintaining error correction capability while reducing the sequential time required for data output.
Solution Approach 2:
The patent introduces a new dimension of encoding by using multiple latch groups that operate in parallel to detect threshold voltage ranges. Instead of sequentially processing each region, the system uses spatial parallelism across multiple latches to achieve simultaneous detection, thereby resolving the timing issues associated with sequential data output.
2Productivity
If the number of data output times is reduced to improve timing, then operational efficiency is improved, but the ability to use multiple regions for error correction deteriorates
Solution Approach 1:
The patent merges the detection functions of multiple latch groups into a unified encoding process. Each latch group detects a specific threshold voltage range, and their combined outputs are encoded together to identify the fail bit region. This merging allows simultaneous utilization of multiple regions while maintaining reduced data output times.
Solution Approach 2:
The latch groups serve multiple functions: they detect threshold voltage ranges, encode region information, and simultaneously contribute to error correction across different memory regions. This multi-functionality allows the system to maintain high region utilization while reducing the number of sequential data output operations.
3Measurement precision
If additional latch circuits are added to recognize infinite ranges, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent assigns specific threshold voltage range detection capabilities to specific latch groups, creating local specialization. Each latch group is optimized to detect a particular range (e.g., first latch group detects first to fourth ranges, second latch group detects fifth to eighth ranges), achieving high measurement precision without requiring a single complex circuit to handle all ranges.
Data Source
AI summary
The present disclosure relates to a semiconductor memory device and a method of operation the semiconductor memory device, which sets an encoding value by sequentially defining ranges used for recognizing distribution of memory cells based on a middle range and then performing a read operation in an order from the middle ranges to an outermost range, thereby capable of using infinite ranges for recognizing the distribution of the memory cells without addition of a circuit to an inside of the semiconductor memory device.