Narrowing Threshold Voltage Distribution in Multi-Bit Nonvolatile Memory
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Solution Overview
Problem
Current nonvolatile memory devices face challenges in managing threshold voltage distributions of multi-bit memory cells, which affects the reliability and efficiency of data storage, especially in high integration levels where error correction and reprogramming techniques are necessary.
Innovation Solution
The method involves performing error checking and correction (ECC) operations on data from a source portion of M-bit nonvolatile memory cells, followed by address-scrambled reprogramming of a target portion using a 2M-1-2M or 2M-2M programming sequence, ensuring that threshold voltages are adjusted without changing the program states, thereby refining the threshold voltage distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-bit memory cells are used to increase integration level, then storage capacity is improved, but threshold voltage distribution management becomes more difficult affecting reliability
Solution Approach 1:
The patent divides the programming process into multiple stages (first programming, second programming, third programming) where each stage programs a specific number of bits (2 bits, then 1 bit, then remaining bits). This segmentation allows manageable control of threshold voltage distribution for each programming stage, improving reliability while achieving multi-bit storage capacity.
Solution Approach 2:
The patent performs preliminary programming of certain bits (first and second bits) before programming the remaining bits. This preliminary action establishes a foundation for threshold voltage distribution that facilitates subsequent programming stages, ensuring reliable multi-bit storage from the outset.
2Reliability
If reprogramming is performed to manage threshold voltage distribution, then reliability is improved, but programming time increases
Solution Approach 1:
The patent segments the reprogramming operation into distinct programming stages, where each stage targets specific bits with optimized programming parameters. This allows efficient management of threshold voltage distribution without requiring complete reprogramming of all bits, reducing overall programming time while maintaining reliability.
Solution Approach 2:
The patent applies different programming strategies to different bits within the same memory cell. Specific bits are programmed with tailored voltage and timing parameters based on their contribution to threshold voltage distribution, optimizing the balance between reliability improvement and programming time.
Data Source
AI summary
Methods of operating memory systems and nonvolatile memory devices include performing error checking and correction (ECC) operations on M pages of data read from a first “source” portion of M-bit nonvolatile memory cells within the nonvolatile memory device to thereby generate M pages of ECC-processed data, where M is a positive integer greater than two (2). A second “target” portion of M-bit nonvolatile memory cells within the nonvolatile memory device is then programmed with the M pages of ECC-processed data using an address-scrambled reprogramming technique, for example.