Memory Module Performance Throttling for Thermal and Buffer Control

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Application-specific integrated circuits (ASICs) face performance degradation due to excess heat and power consumption, which existing technologies fail to effectively manage, leading to hardware-level issues and potential lifespan reduction.

Innovation Solution

The implementation of a digital memory circuit with a media management layer and cache subsystem that monitors and regulates resource demands, employing performance throttling mechanisms based on physical and logical parameters, such as temperature, power consumption, and resource usage, to prevent buffer overflow and reduce heat and power consumption by limiting data read/write requests.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the ASIC processes high volumes of data read/write requests to maintain high productivity, then the processing speed and output increase, but the heat generation and power consumption exceed thresholds causing hardware degradation

Engineering Contradiction:
Improvedata processing throughputVSAvoidASIC operating temperature
Core Design Contradiction:
ProductivityVSTemperature

Solution Approach 1:

The patent implements a feedback mechanism where the system continuously monitors temperature and power consumption levels, and automatically adjusts data processing throughput by throttling requests when thresholds are exceeded. This closed-loop control resolves the contradiction by dynamically balancing productivity against thermal constraints based on real-time system state.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system dynamically adjusts its operating characteristics by varying the acceptance rate of data requests based on current thermal and power conditions. Rather than maintaining fixed high throughput, the system adaptively modulates processing intensity to stay within safe operational boundaries while maximizing productivity when conditions permit.

Inventive Principle:
Principle #15Dynamics

2Quantity of substance

If the ASIC accepts unlimited data read/write requests to maximize processing volume, then the quantity of processed data increases, but buffer overflow errors occur degrading reliability

Engineering Contradiction:
Improvevolume of processed dataVSAvoiderror-free operation
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent applies preliminary action by proactively throttling incoming data requests before the system reaches buffer capacity limits. Rather than allowing buffers to fill to dangerous levels and then correcting errors, the system anticipates potential overflow conditions and preemptively reduces request acceptance rates to maintain reliable operation.

Inventive Principle:
Principle #10Preliminary action

3Power

If the system operates at full power consumption to maintain high performance, then the processing capability is maximized, but the excess power leads to hardware degradation and reduced lifespan

Engineering Contradiction:
Improveprocessing powerVSAvoidASIC operational lifespan
Core Design Contradiction:
PowerVSDuration of action of stationary object

Solution Approach 1:

The system changes operational parameters by adjusting power consumption levels based on monitored conditions. When temperature or error rates indicate stress, the system reduces power usage through request throttling, thereby extending component lifespan. This parameter adjustment resolves the contradiction between maintaining high processing power and preserving long-term reliability.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12164774B2Performance throttling module
Publication Date: 2024.12.10 MICRON TECHNOLOGY INC
  • US12164774B2 patent drawing
  • US12164774B2 patent drawing
  • US12164774B2 patent drawing

AI summary

Provided is a method for regulating, via a hardware performance throttling block (PTB) of a memory module, the performance of a memory system in response to read and write requests from a processing system which hosts the memory system. The host system sends memory service requests to the memory system in the form of memory read requests and memory write requests. The host system sends requests to throttle, that is, to limit the responses of the memory system in response to memory requests; the host system sends to the memory system various parameters indicative of current memory usage. In response to the throttling request, the PTB of the memory module either stops any reception of memory requests, or limits (throttles) the number of memory read requests, write requests, or both for a specified number of clock/command cycles. The PTB also determines when full, un-throttled performance may be resumed.