Nonvolatile Memory Through-Hole Etching via Dual-Rate Insulating Layer

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Solution Overview

Problem

Existing nonvolatile semiconductor memory devices with three-dimensional structures face fluctuations in characteristics due to issues with through-hole configuration and filling processes, leading to voids and increased manufacturing complexity.

Innovation Solution

The implementation of a stacked body with alternating electrode and insulating films, where the insulating layer comprises two portions with different etching rates for dilute hydrofluoric acid, allowing for wider through-holes and improved fillability of semiconductor pillars, reducing the fluctuation of transistor characteristics and manufacturing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional through-hole configuration is used, then manufacturing process is simpler, but fillability of semiconductor pillars is poor and voids form

Engineering Contradiction:

Improvefillability of semiconductor pillarsVSAvoidinsulating layer structure

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The insulating layer is divided into two distinct portions: a first insulating portion and a second insulating portion. This segmentation allows each portion to have different etching rates, enabling precise control of through-hole width at different levels to improve semiconductor pillar fillability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the insulating layer are given different etching rate characteristics. The first insulating portion has a slower etching rate while the second has a faster etching rate, creating local quality variations that maintain larger through-hole inner diameters for better fillability.

Inventive Principle:

Principle #3Local quality

2Reliability

If through-hole width is reduced, then transistor characteristics are more stable, but fillability of semiconductor pillars deteriorates

Engineering Contradiction:

Improvetransistor characteristics stabilityVSAvoidfillability of semiconductor pillars

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The solution addresses the width constraint by introducing a vertical dimension variation through the two-portion insulating layer structure. The through-hole width varies along the vertical axis, being larger in the first portion and smaller in the second portion, thus maintaining stability while improving fillability.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The insulating layer structure is pre-configured with different etching rates before the through-hole formation process. This preliminary action ensures that during etching, the through-hole maintains an optimal width profile that improves fillability while still achieving the required transistor characteristic stability.

Inventive Principle:

Principle #10Preliminary action

3Manufacturing precision

If uniform etching rate is used, then manufacturing process is simpler, but through-hole width cannot be optimized for fillability

Engineering Contradiction:

Improvethrough-hole inner diameterVSAvoidinsulating layer fabrication

Core Design Contradiction:

Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The etching rate parameter is changed across different portions of the insulating layer. By using materials with different etching rates or different thicknesses, the through-hole inner diameter can be optimized for fillability without requiring complex fabrication processes.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the fillability of semiconductor pillars, reduces void formation, and stabilizes the characteristics of memory devices by maintaining a larger inner diameter of through-holes, thereby improving manufacturing efficiency and device performance.

Implementation Method 1

the insulating layer comprises a first insulating portion and a second insulating portion, the etching rate for dilute hydrofluoric acid of the first insulating portion being slower than the etching rate for dilute hydrofluoric acid of the second insulating portion

Methodology Applied

Scientific EffectEtching:

Data Source

PatentUS9627400B2Nonvolatile semiconductor memory device and method for manufacturing same

Publication Date: 2017.04.18 KIOXIA CORP

AI summary

According to one embodiment, a nonvolatile semiconductor memory device includes an interconnect layer, a stacked body, an insulating layer, a semiconductor pillar, a charge storage layer and a first conductive unit. The stacked body is separated from the interconnect layer in a first direction. The stacked body includes a memory unit and a selection gate provided between the memory unit and the interconnect layer. The insulating layer is provided between the interconnect layer and the stacked body. The semiconductor pillar pierces the stacked body in the first direction. The charge storage layer is provided between the semiconductor pillar and the memory unit. The first conductive unit connects the semiconductor pillar and the interconnect layer. A width of the first conductive unit along a second direction perpendicular to the first direction is wider than a width of the semiconductor pillar along the second direction.