Nonvolatile Memory Vertical Structure Through Via Segmentation
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Solution Overview
Problem
Nonvolatile memory devices with three-dimensional structures face performance degradation due to conductive layers with lower conductivity materials, which affect overall device performance.
Innovation Solution
The nonvolatile memory device incorporates a vertical structure with layered pairs of insulating and conductive layers, including polysilicon conductive layers separated by string selection line cuts, and through vias to connect and supply voltage to these layers, enhancing conductivity and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conductive layers with lower conductivity materials are used, then device complexity is reduced and manufacturing is easier, but electrical conductivity and performance deteriorate
Solution Approach 1:
The conductive layer is divided into multiple segments separated by insulating regions. Each segment is independently controlled through through vias connected to pass transistors, allowing selective voltage application. This segmentation enables the use of lower conductivity materials while maintaining overall performance through parallel conduction paths and reduced resistance by distributing current across multiple segments.
Solution Approach 2:
The patent changes the electrical parameters of the conductive layer by applying different voltages to different segments through the through vias and pass transistors. By dynamically adjusting voltage levels and distribution, the effective conductivity of the lower conductivity material is enhanced, allowing it to perform adequately despite its inherent material limitations.
2Quantity of substance
If conductive layers with lower conductivity materials are used, then cost is reduced, but device performance deteriorates
Solution Approach 1:
By segmenting the conductive layer into multiple sections with through vias, the patent enables the use of cost-effective lower conductivity materials while maintaining performance. The segmentation allows parallel current paths that collectively achieve the required conductivity, reducing material costs without sacrificing device productivity.
Solution Approach 2:
The through vias and pass transistors act as intermediaries that compensate for the lower conductivity of the material. By providing additional conduction pathways and voltage control mechanisms, these intermediary structures enable lower conductivity materials to achieve the necessary performance levels, making cost-effective manufacturing possible.
3Reliability
If through vias are added to connect conductive layers, then electrical conductivity is improved, but device complexity increases
Solution Approach 1:
The conductive layer is segmented into multiple sections connected by through vias. This segmentation improves electrical conductivity by creating parallel conduction paths and reducing overall resistance. Although it increases structural complexity, the segmentation enables the use of lower conductivity materials and provides better voltage control.
Solution Approach 2:
The patent introduces vertical connections through through vias that penetrate the insulating layer, adding a vertical dimension to the conductive pathways. This three-dimensional approach to connectivity improves electrical performance by providing multiple conduction routes while managing the complexity through systematic vertical integration.
4Manufacturing precision
If conductive layers are spaced apart to expose insulating layer, then manufacturing precision is improved, but electrical conductivity deteriorates
Solution Approach 1:
The conductive layer is divided into spaced-apart segments separated by insulating regions. This segmentation improves manufacturing precision by allowing independent formation and alignment of each segment. The through vias connect these segments vertically, maintaining electrical conductivity despite the horizontal spacing, thus resolving the contradiction between manufacturing precision and electrical performance.
Solution Approach 2:
By spacing conductive segments apart in the horizontal plane and connecting them through vertical via structures, the patent transitions from two-dimensional planar connectivity to three-dimensional connectivity. This dimensional change allows manufacturing precision to be improved through better segment alignment while maintaining electrical conductivity through the vertical connection paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration maintains performance by reducing resistance and ensuring effective voltage supply to conductive layers with lower conductivity, thereby preventing performance reduction.
Implementation Method 1
the second conductive layer and the third conductive layer are connected with a first through via that penetrates the second active region, the vertical structure and the region of the second insulating layer that is exposed between the second conductive layer and the third conductive layer
Data Source
AI summary
A nonvolatile memory device includes a peripheral circuit including a first active region and a memory block including a second active region on the peripheral circuit. The memory block includes a vertical structure including pairs of a first insulating layer and a first conductive layer, a second insulating layer on the vertical structure, a second conductive layer and a third conductive layer spaced apart from each other on the second insulating layer, first vertical channels and second vertical channels. The second conductive layer and the third conductive layer are connected with a first through via penetrating the vertical structure, the second active region, and a region of the second insulating layer that is exposed between the second conductive layer and the third conductive layer.