Memory Channel TID Synchronization Using ECC and CRC Parity
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Solution Overview
Problem
In DDR memory channels, synchronizing transaction identifications (TIDs) between the host and memory devices without additional bus resources is challenging, especially when embedding TID information increases channel overhead and errors in TID detection occur, particularly in noisy memory environments.
Innovation Solution
A communication method that generates TIDs using incremental counters and embeds parity bits into error-correcting codes (ECCs) for write transactions and cyclic redundancy check (CRC) codes for read transactions, allowing for error detection and correction, and retransmission of commands to ensure synchronization and data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TID information is embedded into CRC bytes of DDR4, then TID synchronization is achieved, but channel overhead increases from 12.5% to 40.625%
Solution Approach 1:
The patent combines TID synchronization with existing ECC and CRC mechanisms by merging TID bits into the least significant bits of command and address fields. This integration allows TID information to be transmitted without requiring separate dedicated bits, thereby achieving synchronization while minimizing additional overhead.
Solution Approach 2:
The patent makes existing bus resources multi-functional by using the same command and address fields to carry both traditional control information and TID synchronization information. The least significant bits of these fields serve dual purposes: maintaining their original control functions while simultaneously encoding TID data for synchronization.
2Reliability
If TID is reported by read data's ECC as interrupt, then error detection is achieved, but additional handshaking pins are required
Solution Approach 1:
The patent merges TID error reporting with the existing data bus by embedding TID information and its error status within the read data payload and associated CRC/ECC fields. This eliminates the need for separate handshaking pins, as the same data path carries both the data and the TID synchronization information.
Solution Approach 2:
The patent enables the read data bus to serve multiple functions: transmitting data, carrying TID information, and reporting TID errors through the existing CRC/ECC mechanisms. This multi-functionality removes the need for additional dedicated error reporting pins.
3Device complexity
If incremental counter is used for TID generation, then TID assignment is simplified, but synchronization between host and device becomes challenging
Solution Approach 1:
The patent implements feedback mechanisms where the device controller monitors and compares its locally generated TID sequence with the host's TID assignments. When discrepancies are detected, the device adjusts its counter to realign with the host, ensuring continuous synchronization while maintaining the simplicity of incremental counter generation.
Solution Approach 2:
The patent dynamically adjusts parameters of the incremental counter, such as the starting value or increment step, based on synchronization status. This allows the counter to adapt to different operational modes and maintain alignment with the host without requiring complex assignment logic.
Data Source
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AI summary
Various embodiments include methods and apparatus structured to provide synchronization of a transaction identification between a host and a memory module using a parity check. A transaction identification can be generated at both the host and the memory module independently using incremental counters of these apparatus. Synchronization of the transaction identifications generated by the host and by a controller of the memory module can be implemented using a parity bit sequences pattern of a combination of the generated transaction identification plus the corresponding transaction command and data address. Use of transaction commands modified with respect to transaction identifications can be used in initialization of the synchronization, in message passing, and in error detection and response to errors. Additional apparatus, systems, and methods can be implemented in a variety of applications.