Memory Channel TID Synchronization Using Parity-Based Error Detection
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Solution Overview
Problem
Current methods for synchronizing transaction identifications (TIDs) in DDR memory channels, such as DDR4 or DDR5, face challenges in efficiently handling TID assignments and errors without additional bus resources, leading to high channel overhead and late error detection in read transactions.
Innovation Solution
A communication method that generates TIDs using incremental counters and embeds parity bits into error-correcting codes (ECCs) for write transactions, allowing for error detection and retransmission over noisy memory channels, and uses cyclic redundancy check (CRC) codes for read transactions to ensure accurate data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TID information is embedded into current CRC bytes of DDR4, then TID synchronization is achieved, but channel overhead increases from 12.5% to 40.625%
Solution Approach 1:
The patent extracts TID synchronization from the CRC byte embedding approach and implements it through a separate parity bit mechanism. The host and device controllers independently generate TIDs using incremental counters, and synchronization is achieved through parity bit comparison rather than embedding TID information in existing CRC bytes, thereby avoiding the 40.625% overhead increase.
Solution Approach 2:
The patent makes the existing parity bit mechanism universal by having it serve dual purposes: traditional error detection and TID synchronization. The parity bit is generated from both the data and the TID, allowing a single bit to perform multiple functions without requiring additional channel resources.
2Loss of time
If TID is synced to the received read request, then error detection timing is improved, but additional bus resources are required
Solution Approach 1:
The patent merges TID synchronization with the existing read request processing flow. The device controller generates the TID independently using an incremental counter and compares it with the host's TID through parity bit comparison during the normal read transaction, eliminating the need for separate synchronization bus resources while achieving timely error detection.
Solution Approach 2:
The system uses self-service by having both host and device controllers independently generate TIDs using their own incremental counters. The synchronization is achieved through mutual comparison of these independently generated TIDs via parity bits, without requiring external arbitration or additional control bus resources.
3Reliability
If three handshaking pins are used as shared feedback error message bus, then error feedback is achieved, but device complexity increases
Solution Approach 1:
The patent uses the existing parity bit as an intermediary to convey TID synchronization status and error information. Instead of requiring three dedicated handshaking pins for error feedback, the parity bit serves as a mediator that carries both error detection and TID synchronization information through the existing data path.
Data Source
AI summary
Various embodiments include methods and apparatus structured to provide synchronization of a transaction identification between a host and a memory module using a parity check. A transaction identification can be generated at both the host and the memory module independently using incremental counters of these apparatus. Synchronization of the transaction identifications generated by the host and by a controller of the memory module can be implemented using a parity bit sequences pattern of a combination of the generated transaction identification plus the corresponding transaction command and data address. Use of transaction commands modified with respect to transaction identifications can be used in initialization of the synchronization, in message passing, and in error detection and response to errors. Additional apparatus, systems, and methods can be implemented in a variety of applications.