3D Memory Read Mode Selection for Tier Boundary Reliability
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Solution Overview
Problem
The reliability of read operations in three-dimensional memory systems with stacked word lines is compromised due to manufacturing methods that result in varying dimensions of memory pillars, leading to increased machining difficulty and error bits near tier boundaries, which can reduce data read accuracy and performance.
Innovation Solution
Implementing an adjacent-word-line compensation read mode selectively for memory cells near tier boundaries, while using typical read modes for cells farther away, to enhance data read reliability without unnecessarily increasing read time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells near tier boundaries are read using typical read modes, then read operation speed is maintained, but data read reliability deteriorates due to increased error bits caused by varying memory pillar dimensions
Solution Approach 1:
The patent applies different read modes to different regions of the memory cell array. Specifically, memory cells near tier boundaries (where manufacturing variations cause larger errors) use adjacent-word-line compensation read mode, while memory cells farther from tier boundaries use typical read modes. This localized approach improves reliability where needed without sacrificing overall read performance.
Solution Approach 2:
The memory cell array is segmented into different regions based on proximity to tier boundaries. The controller identifies and separates memory cells that require compensation reads from those that do not, allowing selective application of different read modes to different segments of the memory array.
2Reliability
If adjacent-word-line compensation read mode is applied to all memory cells, then data read reliability is improved, but read operation speed deteriorates due to increased read time
Solution Approach 1:
The patent applies adjacent-word-line compensation read mode only to memory cells near tier boundaries where manufacturing variations are most significant, rather than uniformly to all memory cells. This selective application maintains high reliability for problematic cells while preserving fast read performance for the majority of cells that do not require compensation.
Solution Approach 2:
Instead of applying the more time-consuming compensation read mode to all memory cells (excessive action), the patent applies it only partially to those cells that actually need it (near tier boundaries), thereby achieving the necessary reliability improvement without the full performance penalty.
3Manufacturing precision
If memory pillars are manufactured with consistent dimensions, then manufacturing precision is improved, but machining difficulty increases due to the complexity of maintaining uniform dimensions across tier boundaries
Solution Approach 1:
Rather than attempting to manufacture all memory pillars with identical dimensions (which would be extremely difficult), the patent accepts that dimensions will vary, particularly near tier boundaries. Instead, it compensates for these variations through software-based read mode selection and error correction, effectively addressing the precision issue without requiring prohibitively complex manufacturing processes.
Solution Approach 2:
The patent converts the harmful effect of manufacturing variations (which create larger errors near tier boundaries) into a manageable problem by using these variations as a basis for selective read mode application. The controller identifies affected regions and applies compensation reads only where needed, turning a manufacturing defect into a controllable parameter.
Data Source
AI summary
A memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes memory cells at intersection locations of stacked word lines and a memory pillar passing through the word lines in a stacking direction, the word lines including a first group of word lines stacked above a second group of word lines. The controller reads data of a first memory cell in a first read mode and reads data of a second memory cell in a second read mode. The first memory cell is, and the second memory cell is not, at an intersection location of a word line that is in a boundary area of the first and second groups of word lines and the memory pillar. The boundary area is adjacent to a location of the memory pillar where a width of the memory pillar discontinuously changes along the stacking direction.