Memory Tier Segregation for Data Access Optimization

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional memory systems face challenges in optimizing data access performance due to differences in data access speeds and operating characteristics across various memory tiers, leading to inefficiencies in cache hit ratios and memory utilization.

Innovation Solution

The implementation of a data stream segregation technique that separates data streams based on access patterns and frequencies, using a prediction model to optimize data placement across different memory tiers, including volatile and non-volatile memory components, to improve overall system performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data is stored in faster memory tiers to improve data access speed, then data access speed is improved, but memory cost and energy consumption increase

Engineering Contradiction:
Improvedata access speedVSAvoidmemory energy consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent segments data streams into multiple categories based on access patterns (frequently accessed, moderately accessed, rarely accessed) and assigns each category to appropriate memory tiers. This segmentation allows the system to optimize for speed where needed while conserving energy in less critical areas, resolving the contradiction between data access speed and energy consumption.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by providing different memory quality levels to different data based on their access characteristics. Frequently accessed data receives high-quality fast memory placement, while rarely accessed data is placed in lower-quality slower memory, ensuring that energy resources are allocated efficiently according to local data requirements rather than uniformly across all data.

Inventive Principle:
Principle #3Local quality

2Speed

If data is stored in faster memory tiers to improve data access speed, then data access speed is improved, but memory cost increases

Engineering Contradiction:
Improvedata access speedVSAvoidmemory cost
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The patent segments the data storage system into multiple tiers with different cost characteristics, placing only the necessary portion of data in expensive fast memory while storing the remainder in cheaper slower memory. This segmentation strategy maintains high data access speed for critical data while significantly reducing overall memory cost compared to storing all data in fast memory.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by matching memory quality to data value, ensuring that expensive fast memory resources are allocated only to data that requires high-speed access, while less critical data resides in cheaper memory tiers. This optimizes the trade-off between data access speed and memory cost by applying quality differentiation locally to individual data streams.

Inventive Principle:
Principle #3Local quality

3Device complexity

If mixed data streams are processed together in conventional memory systems, then memory utilization is simplified, but data access performance deteriorates due to different access patterns

Engineering Contradiction:
Improvememory management complexityVSAvoiddata access performance
Core Design Contradiction:
Device complexityVSSpeed

Solution Approach 1:

The patent segments mixed data streams into separate categorized streams based on access patterns, allowing each stream to be managed independently with optimization strategies tailored to its specific characteristics. This segmentation improves data access performance by preventing fast-access data from being blocked by slow-access data operations, while the overall system remains manageable through automated classification mechanisms.

Inventive Principle:
Principle #1Segmentation

4Reliability

If data is frequently moved between memory tiers to optimize cache hit ratios, then cache hit ratio is improved, but system performance deteriorates due to data movement overhead

Engineering Contradiction:
Improvecache hit ratioVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies preliminary action by proactively classifying and placing data in appropriate memory tiers based on predicted access patterns before actual access occurs. The data stream segregation system uses analysis of access characteristics to pre-position data in optimal memory locations, reducing the need for reactive data movement and thereby improving cache hit ratios without significant performance overhead.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback mechanisms that monitor data access patterns and dynamically adjust data placement decisions. By continuously observing access characteristics and feeding this information back to the data stream segregation logic, the system optimizes cache hit ratios adaptively while minimizing unnecessary data movement, thus maintaining high system performance.

Inventive Principle:
Principle #23Feedback

Data Source

PatentEP3750072B1Accelerate data access in memory systems via data stream segregation
Publication Date: 2024.10.30 MICRON TECHNOLOGY INC
  • EP3750072B1 patent drawingFigure 1
  • EP3750072B1 patent drawingFigure 2
  • EP3750072B1 patent drawingFigure 3

AI summary

A computing system having memory components of different tiers. The computing system further includes a processing device, operatively coupled to the memory components, to: receive data access requests; generate a plurality of data access streams in accordance with the data access requests and access characteristics of the request; match characteristics of the data access streams with characteristics of the different tiers of the memory components; and direct the plurality of data access streams to the different tiers of the memory components based on matching the characteristics of the data access streams with the characteristics of the different tiers of the memory components.